
    <<SCB>>
        <<Copyright © 1986 by Xerox Corporation.  All rights reserved.>>
        <<Created: Douady, Sindhu May 13, 1987 3:05:39 pm PDT>>
        <<Cesar Douady May 13, 1987 3:06:50 pm PDT>>
        <<Pradeep Sindhu June 17, 1987 12:59:36 pm PDT>>
    <<>>
    <<Contains the Bus-side microcode. It models only the combinatorial part. The complete model is in BCtl.sch.>>

    DIRECTORY
        Core, CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, SCB
    <<>>

    SCB
    IMPORTS CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary
    EXPORTS SCB
    ~ BEGIN OPEN SCB

        MaxNumSignals: NAT = 100;
        Xs: NAT = LAST[NAT];
        ToBeDefined: NAT = Xs;

        IndexType: TYPE = {dummyIndex};

        Index: ARRAY IndexType OF NAT;

        SignalType: TYPE = {Input, Output, Power};

        Signals: TYPE = REF SignalsRec;
        SignalsRec: TYPE = RECORD [
            SEQUENCE size: NAT OF RECORD [
                name: ROPE _ NIL,
                size: NAT _ 0,
                st: SignalType,
                default: Level _ X,
                defaultS: NAT _ Xs,
                index: NAT _ Xs
                ]
            ];

        <<The signals:>>
        <<The declaration below simply creates signals, putting signal foo's characteristics in signals[foo]>>

        signals: Signals _ NEW [SignalsRec[MaxNumSignals]];

        numSignals: NAT _ 0;

        ARM: NAT = Declare["ARM", X, Input];
        BIOWRqst: NAT = Declare["BIOWRqst", X, Input];
        CWSRply: NAT = Declare["CWSRply", X, Input];
        CWSRplyandARM7: NAT = Declare["CWSRplyandARM7", X, Input];
        IdMatch: NAT = Declare["IdMatch", X, Input];
        IORRqst: NAT = Declare["IORRqst", X, Input];
        IOTIdMatch: NAT = Declare["IOTIdMatch", X, Input];
        IOWRqst: NAT = Declare["IOWRqst", X, Input];
        RBRqst: NAT = Declare["RBRqst", X, Input];
        RBRply: NAT = Declare["RBRply", X, Input];
        RplyStale: NAT = Declare["RplyStale", X, Input];
        WBRqst: NAT = Declare["WBRqst", X, Input];
        WSRply: NAT = Declare["WSRply", X, Input];

        <<Reset: NAT = Declare["Reset", X, Input];>>

        BCtlEnRamSel4: NAT = Declare["BCtlEnRamSel4", X, Output];
        BCtlLdFIFOAOw4: NAT = Declare["BCtlLdFIFOAOw4", X, Output];
        BCtlLdFIFOnAOw4: NAT = Declare["BCtlLdFIFOnAOw4", X, Output];
        BCtlRamForBCWS4: NAT = Declare["BCtlRamForBCWS4", X, Output];
        BCtlRdRam4: NAT = Declare["BCtlRdRam4", X, Output];
        BCtlRPValid4: NAT = Declare["BCtlRPValid4", X, Output];
        BCtlSelBCWS4: NAT = Declare["BCtlSelBCWS4", X, Output];
        BCtlSelRRdLatch4: NAT = Declare["BCtlSelRRdLatch4", X, Output];
        BCtlSelWdData4: NAT = Declare["BCtlSelWdData4", X, Output];
        BCtlSelWSData4For67: NAT = Declare["BCtlSelWSData4For67", X, Output];
        BCtlSelWSData7For910: NAT = Declare["BCtlSelWSData7For910", X, Output];
        BCtlVPValid4: NAT = Declare["BCtlVPValid4", X, Output];
        BCtlWtRam47: NAT = Declare["BCtlWtRam47", X, Output];
        CWSRplyandARM4: NAT = Declare["CWSRplyandARM4", X, Output];

        Vdd: NAT = Declare["Vdd", X, Power];
        Gnd: NAT = Declare["Gnd", X, Power];
<<Public Procs>>

    Create: PUBLIC PROC [] RETURNS [ct: CellType] = {
        nameList: LIST OF CoreCreate.WR _ NIL;

        FOR i: NAT IN [0..numSignals) DO
            IF signals[i].name=NIL THEN LOOP;
            IF signals[i].size=0
                THEN nameList _ CONS[signals[i].name, nameList]
                ELSE nameList _ CONS[CoreCreate.Seq[signals[i].name, signals[i].size], nameList]
            ENDLOOP;
        ct _ CoreClasses.CreateUnspecified[public: CoreCreate.WireList[nameList, b

        [] _ Rosemary.BindCellType[cellType: ct, roseClassName: b
        [] _ CoreFlat.CellTypeCutLabels[ct, "Logic"];

        FOR i: NAT IN [0..numSignals) DO
            IF signals[i].name=NIL THEN LOOP;
            signals[i].index _ Ports.PortIndex[ct.public, signals[i].name];
            ENDLOOP;

        FOR i: NAT IN [0..numSignals) DO
            SwitchType: TYPE = RECORD [BOOL, SignalType];
            switch: SwitchType _ [signals[i].size=0, signals[i].st];

            IF signals[i].name=NIL THEN LOOP;
            SELECT switch FROM
                [TRUE, Input]    => [] _ Ports.InitPorts[ct, l, none, signals[i].name];    
                [TRUE, Output]    => [] _ Ports.InitPorts[ct, l, drive, signals[i].name];
                [TRUE, Power]    => [] _ Ports.InitPorts[ct, b, none, signals[i].name];
                [FALSE, Input]    => [] _ Ports.InitPorts[ct, ls, none, signals[i].name];
                [FALSE, Output]    => [] _ Ports.InitPorts[ct, ls, drive, signals[i].name];
                ENDCASE => ERROR;
            ENDLOOP;
        };

    Init: Rosemary.InitProc = {
        <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->>
        };

    Simple: Rosemary.EvalProc = {
        <<--PROC [p: Ports.Port, stateAny: REF ANY]-->>

    XInInputs: PROC [] RETURNS [BOOL _ FALSE] = {
        FOR i: NAT IN [0..numSignals) DO
            IF signals[i].name=NIL OR signals[i].st#Input THEN LOOP;
            IF signals[i].size=0
                THEN {IF p[signals[i].index].l=X THEN RETURN[TRUE]}
                ELSE {IF XInLS[p[signals[i].index].ls] THEN RETURN[TRUE]}
            ENDLOOP;
    };

    OutputsToX: PROC [] = {
        FOR i: NAT IN [0..numSignals) DO
            IF signals[i].name=NIL OR signals[i].st#Output THEN LOOP;
            IF signals[i].size=0
                THEN p[signals[i].index].l _ X
                ELSE Ports.SetLS[p[signals[i].index].ls, X]
            ENDLOOP;
    };

    OutputsToDefault: PROC [] = {
        FOR i: NAT IN [0..numSignals) DO
            IF signals[i].name=NIL OR signals[i].st#Output THEN LOOP;
            IF signals[i].size=0
                THEN p[signals[i].index].l _ signals[i].default
                ELSE Ports.LCToLS[signals[i].defaultS, p[signals[i].index].ls]
            ENDLOOP;
    };

    v: PROC [ix: NAT] RETURNS [BOOL] = {
    RETURN[p[signals[ix].index].l=H]
    };

    vs: PROC [ix: NAT] RETURNS [NAT] = {
    RETURN[Ports.LSToLC[p[signals[ix].index].ls]]
    };

    s: PROC [ix: NAT, l: Level] = {
    p[signals[ix].index].l _ l
    };

    sb: PROC [ix: NAT, l: BOOL] = {
    p[signals[ix].index].l _ IF l THEN H ELSE L
    };

    ss: PROC [ix: NAT, c: CARD] = {
        IF c=Xs
            THEN Ports.SetLS[p[signals[ix].index].ls, X]
            ELSE Ports.LCToLS[c, p[signals[ix].index].ls];
    };


    OutputsToDefault[];

        <<The microcode >>
    IF XInInputs[] THEN {OutputsToX[]; RETURN};
    sb[BCtlSelWSData4For67,
    (v[WSRply] OR v[IOWRqst] AND v[IOTIdMatch] OR v[BIOWRqst]) AND v[ARM]
    ];
    sb[BCtlSelWSData7For910,
    v[CWSRplyandARM7]
    ];
    sb[BCtlSelBCWS4,
    v[CWSRply] AND v[ARM]
    ];
    sb[BCtlRamForBCWS4,
    v[CWSRply] AND v[ARM]
    ];
    sb[BCtlWtRam47,
    (v[WSRply] OR v[IOWRqst] AND v[IOTIdMatch] OR v[BIOWRqst] OR v[WBRqst]) AND v[ARM] OR v[RBRply] AND v[IdMatch] OR v[CWSRplyandARM7]
    ];
    sb[BCtlEnRamSel4,
    ((v[WSRply] OR v[IOWRqst] AND v[IOTIdMatch] OR v[BIOWRqst] OR v[WBRqst]) AND v[ARM] OR v[RBRply] AND v[IdMatch] OR 
    v[CWSRplyandARM7]) OR ((v[RBRqst] OR v[IORRqst] AND v[IOTIdMatch] OR v[CWSRply]) AND v[ARM])
    ];
    sb[BCtlRdRam4,
    (v[RBRqst] OR v[IORRqst] AND v[IOTIdMatch] OR v[CWSRply]) AND v[ARM]
    ];
    sb[BCtlSelWdData4,
    (v[WSRply] OR (v[IORRqst] OR v[IOWRqst]) AND v[IOTIdMatch] OR v[BIOWRqst] OR v[CWSRply]) AND v[ARM] OR v[CWSRplyandARM7]
    ];
    sb[BCtlLdFIFOAOw4,
    v[RBRqst] AND v[ARM]
    ];
    sb[BCtlLdFIFOnAOw4,
    (v[IORRqst] OR v[IOWRqst]) AND v[IOTIdMatch] AND v[ARM]
    ];
    sb[BCtlSelRRdLatch4,
    v[CWSRply] AND v[ARM]
    ];
    sb[CWSRplyandARM4,
    v[CWSRply] AND v[ARM]
    ];
    sb[BCtlVPValid4,
    v[RBRply] AND v[IdMatch] AND ~v[RplyStale]
    ];
    sb[BCtlRPValid4,
    v[RBRply] AND v[IdMatch]
    ];
        };

<<Internal Procs>>

    Next: PROC [it: IndexType] RETURNS [index: NAT] = {
        index _ Index[it];
        Index[it] _ Index[it]+1;
        };

    Declare: PROC [name: ROPE, default: Level, st: SignalType] RETURNS [ix: NAT] = {
        signals[numSignals] _ [name: name, st: st, default: default];
        ix _ numSignals;
        numSignals _ numSignals+1;
        };

    DeclareS: PROC [name: ROPE, size: NAT, defaultS: CARD, st: SignalType] RETURNS [ix: NAT] = {
        signals[numSignals] _ [name: name, size: size, st: st, defaultS: defaultS];
        ix _ numSignals;
        numSignals _ numSignals+1;
        };

    XInLS: PROC [ls: LevelSequence] RETURNS [BOOL _ FALSE] = {
        FOR i: NAT IN [0..ls.size) DO IF ls[i]=X THEN RETURN [TRUE] ENDLOOP;
        };

    b


    <<RosemaryUser.RegisterTestProc["Test", Test];>>
    END.