This document derives the timing model used in the design of the small cache. The assumptions, calculations, and simulations used in coming up with the model are also contained herein.

We assume that the array CAM is two ported to avoid P/M conflicts, while the RAM is single ported. Single porting the RAM drastically reduces the area without cutting down on performance because M accesses to the RAM are relatively rare. Given this structure there are two major alternatives for the timing of the array:

Alternative A. suffers from two problems. First, since RCAM and VCAM match lines will be discharged on the same phase, the peak currents will be twice those for alternative B. Second, giving priority to the M side for RAM accesses is more complicated: to prevent the P side accessing the RAM when the M side wants it we would need to gate the connection of VMatch to RAMSelect with nArrayRMatch. This signal is the OR of all the RMatch lines, and takes longer to compute than any of the match lines. Thus we end up putting extra computation in the critical path (from address available to RAMSelect)—something that is undesirable. Its possible to avoid this critical path by slowing down the M side accesses by one more cycle, as follows

This is fine for a slow M-Bus, but unacceptable for a faster one.

Thus the timing for the array will be as follows:

There are two contributions to the CAM bit line capacitance: a capacitance attached directly to the bit line, and a capacitance connected to the bit line via an on transistor. The directly attached capacitance is fixed, while the connected capacitance depends on the number of transistors in the array that happen to be on.

The match line runs through 32 cells where it is connected to something and flies over 32 other cells.

The computation below assumes that the piece of diffusion covering the via is removed to make the capacitance as small as possible. This increases the height of the cell by about a micron or so but decreases the capacitance by 30%.