Small Cache Description RCam Real Cam. Matches DynaBus addresses. VCam Virtual Cam. Matches processor addresses. The two Cams together implement the virtual to real mapping. Victim Contains relatively autonomous hardware for victim selection. ArrayCtl Contains muxes and control to drive the Cam and Ram select lines. SO Blk Contains the shared and owner bits; these are accessed using the Ram select lines. Ram Contains the data. Each line contains 256 bits; two lines of Ram correspond to one line of Cam. Reply Reg Contains the header cycle for a reply packet. PSend Reg Contains the header cycle for a request packet. Block Assembly Reg Puts the four cycles of data for an incoming packet into the proper place for storing. RqstAdrs Logic Contains an address register and two bits: stale and sharedAccumulator. Used by the consistency algorithm. Hdr FIFO Contains header cycles waiting to be sent. Block FIFO Contains data cycles waiting to be sent; each entry is up to one block. Output Logic Does bus request; pulls out data from the FIFOs and dumps it onto the bus; fairly autonomous. Timing Real Match in one cycle; ArrayRealMatch in < 2 cycles. Virtual Match in one cycle; ArrayVirtualMatch in < 2 cycles. Ram Read/Ram Write in two cycles. RCam Read in three cycles. RCam/VCam Write in two cycles. Ê›˜title˜head˜Ibody˜$—˜M˜f—˜M˜=—˜M˜A—˜M˜R—˜M˜_—˜ M˜-—˜ M˜/—˜M˜V—˜M˜j—˜M˜*—˜ M˜G—˜M˜]—˜M˜6M˜