SmallCacheTiming.tioga
Written by: Pradeep Sindhu, March 24, 1986 1:42:03 pm PST
Last Edited by:
Pradeep Sindhu, April 8, 1988 4:55:33 pm PDT
DRAGON SMALL CACHE CAPACITANCES FOR TIMING SIMULATION AND TRANSISTOR SIZING
DRAGON SMALL CACHE CAPACITANCES FOR TIMING SIMULATION AND TRANSISTOR SIZING
DRAGON SMALL CACHE CAPACITANCES FOR TIMING SIMULATION AND TRANSISTOR SIZING
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
Dragon Small Cache
Capacitances for Timing Simulation and Transistor Sizing
Release as [Indigo]<Dragon>SmallCache>Documentation>SmallCacheTiming.tioga, .press
© Copyright 1985 Xerox Corporation. All rights reserved.
Abstract: This document describes the timing model used in the small cache's design. It also contains the calculations, assumptions, and Thyme simulations needed to support this model.
XEROX Xerox Corporation
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3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
Contents
Introduction
Appendix A: CAM Bit Line Capacitance
Appendix B: CAM Match Line Capacitance
Appendix C: RAM Bit Line Capacitance
Introduction
This document derives the timing model used in the design of the small cache. The assumptions, calculations, and simulations used in coming up with the model are also contained herein.
Appendix A: CAM Bit Line Capacitance
There are two contributions to the CAM bit line capacitance: a capacitance attached directly to the bit line, and a capacitance connected to the bit line via an on transistor. The directly attached capacitance is fixed, while the connected capacitance depends on the number of transistors in the array that happen to be on. Two alternatives will be considered. Alternative (A) corresponds to a CAM cell with two 8/2 match pulldowns. Alternative (B) corresponds to a CAM cell with two 4/2 match pulldowns.
(A and B) Directly Connected Capacitance (Per Cell) C
d
80mx4m metal2 wire (0.01)*70/100=0.008pF
50m2 diffusion area (1.5 E-4)*55.5=0.008pF
32m diffusion sidewall (3 E-4)*32=0.01pF
Total capacitance 0.026pF
(A) Capacitance Connected Via 4/2 N-type Transistor (9K Ohms) C
c
50m2 diffusion area (1.5 E-4)*50=0.008pF
42m diffusion sidewall (3 E-4)*50=0.013pF
9mx4m metal1 wire (0.01)*9/100=0.001pF
36m2 poly area (0.78 E-4)*36=0.003pF
32m2 gate capacitance (12 E-4)*32=0.038pF
8m2 gate capacitance (on transistor) (12 E-4)*8=0.009pF
Total capacitance 0.072pF
(B) Capacitance Connected Via 4/2 N-type Transistor (9K Ohms) C
c
50m2 diffusion area (1.5 E-4)*50=0.008pF
42m diffusion sidewall (3 E-4)*50=0.013pF
9mx4m metal1 wire (0.01)*9/100=0.001pF
54m2 poly area (0.78 E-4)*54=0.003pF
16m2 gate capacitance (12 E-4)*16=0.019pF
8m2 gate capacitance (on transistor) (12 E-4)*8=0.009pF
Total capacitance 0.053pF
Total Impedance for numMemLines Cache Lines
Let numMemLines be the number of cache lines and N be the number of 4/2 N-type transistors that are on. Then the total direct capacitance is numMemLines/2*Cd, the total connecting resistance is 9000/N, and the total connected capacitance is N*Cc. The number of on transistors N satisfies 0dNdnumMemLines/2. For the total direct capacitance, we're assuming a CAM-RAM-CAM layout, where the height of the array is numMemLines/2 times the height of a CAM cell (or numMemLines times the height of a RAM cell).
For numMemLines=75 lines the figures are:
(A, B) direct capacitance 1.9pF
(A) connected capacitance 0 to 5.4pF
(B) connected capacitance 0 to 4.0pF
connection resistance to 120Ohms
Appendix B: CAM Match Line Capacitance
The match line runs through 32 cells where it is connected to something and flies over 32 other cells.Two alternatives will be considered. Alternative (A) corresponds to a CAM cell with two 8/2 match pulldowns. Alternative (B) corresponds to a CAM cell with two 4/2 match pulldowns.
(A) Capacitance for Connected Cells
28mx3m metal1 wire (0.01)*28/100=0.0028pF
64m2 diffusion area (1.5 E-4)*64=0.01pF
52m diffusion sidewall (3 E-4)*52=0.016pF
Total capacitance 0.028pF
(B) Capacitance for Connected Cells
28mx3m metal1 wire (0.01)*28/100=0.0028pF
40m2 diffusion area (1.5 E-4)*40=0.006pF
36m diffusion sidewall (3 E-4)*36=0.011pF
Total capacitance 0.019pF
Capacitance for FlyOver Cells
28mx3m metal1 wire (0.01)*28/100=0.0028pF
Total capacitance 0.0028pF
Total Capacitance for Match Line
Total capacitances are
(A) 32*0.028+32*0.0028pF = 0.98pF
(B) 32*0.019+32*0.0028pF = 0.69pF.
Appendix C: RAM Bit Line Capacitance
The computation below assumes that the piece of diffusion covering the via is removed to make the capacitance as small as possible. This increases the height of the cell by about a micron or so but decreases the capacitance by 30%.
Bit Line Capacitance (per cell) C
40mx4m metal2 wire (0.01)*40/100=0.004pF
20m2 N-diffusion area (1.5 E-4)*20m2=0.003pF
15m N-diffusion sidewall (3 E-4)*15m=0.0045pF
Total capacitance 0.0115pF
Total Capacitance for numMemLines Cache Lines
The the total capacitance is 2*numMemLines*C.
For numMemLines=75 the figure is: 1.73pF
Appendix D: RAM Select Line Capacitance
Select Line Capacitance (per cell) C
26mx3m metal1 wire (0.01)*26/100=0.0026pF
20m2 poly area (0.78 E-4)*20m2=0.0016pF
16m2 gate capacitance (12 E-4)*16m2=0.0188pF
Total capacitance 0.023pF
Total Capacitance for 256 Cells
0.023*256=5.8pF
Appendix E: Capacitance of Match Latch Load Lines and Clamp Line
nLdML Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008pF
32m2 gate capacitance (12 E-4)*32m2=0.0384pF
Total capacitance 0.046pF
LdML Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008pF
16m2 gate capacitance (12 E-4)*16m2=0.0188pF
Total capacitance 0.027pF
ClampMatch Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008 pF
32m2 gate capacitance (12 E-4)*32m2=0.0384 pF
Total capacitance 0.046 pF
nArrayMatch Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008 pF
144 m2 diffusion capacitance (1.5 E-4)*144 m2=0.0216 pF
72 m diffusion sidewall capacitance (3.0 E-4)*72 m2=0.0216 pF
Total capacitance 0.0512 pF
Total nLdML Line Capacitance = 0.046*75Lines = 3.5 pF
Total LdML Line Capacitance = 0.027*75Lines = 2.0 pF
Total ClampMatch Line Capacitance = 0.046*75Lines = 3.5 pF
Total nArrayMatch Line Capacitance = 0.046*75Lines = 3.8 pF
Appendix F: Capacitance of RSMux and CSMux Control Lines
nDCmd Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008pF
32m2 gate capacitance (12 E-4)*32m2=0.0384pF
Total capacitance 0.046pF
DCmd Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008pF
16m2 gate capacitance (12 E-4)*16m2=0.0188pF
Total capacitance 0.027pF
EnCS and EnCSExt Line Capacitance (per cell)
80mx4m metal2 wire (0.01)*80/100=0.008 pF
64 m2 gate capacitance (12 E-4)*16m2=0.0768 pF
Total capacitance 0.0848 pF
Total nDCmd Line Capacitance = 0.046*75 Lines = 3.5 pF
Total DCmd Line Capacitance = 0.027*75 Lines = 2.0 pF
Total EnCS and EnCSExt Line Capacitance = 0.0848*75 Lines = 6.4 pF
Appendix G: Capacitance of Victim Control Lines
Clock and nClock Line Capacitances (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
48 m2 gate capacitance (12 E-4)*48 m2=0.0576 pF
Total capacitance 0.0656 pF
LdUse and
ShftVictim Line Capacitances (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
16 m2 gate capacitance (12 E-4)*16 m2=0.0192 pF
Total capacitance 0.0272 pF
Reset Line Capacitance (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
8 m2 gate capacitance (12 E-4)*8 m2=0.0096 pF
Total capacitance 0.0176 pF
ResetR Line Capacitance (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
8 m2 gate capacitance (12 E-4)*8 m2=0.0096 pF
Total capacitance 0.0176 pF
nReset Line Capacitance (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
20 m2 gate capacitance (12 E-4)*20 m2=0.024 pF
Total capacitance 0.032 pF
nCOut Line Capacitance (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
16 m2 gate capacitance (12 E-4)*16 m2=0.0192 pF
Total capacitance 0.0272 pF
FrzVictim and nFrzVictim Line Capacitances (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
24 m2 gate capacitance (12 E-4)*128 m2=0.0288 pF
Total capacitance 0.0368 pF
nAVct Line Capacitances (per cell) C
80mx4m metal2 wire (0.01)*80/100=0.008 pF
144 m2 diffusion capacitance (1.5 E-4)*144 m2=0.0216 pF
72 m diffusion sidewall capacitance (3.0 E-4)*72 m2=0.0216 pF
Total capacitance 0.0512 pF
Total Clock and nClock Line Capacitances = 0.0656*75 Lines = 4.9 pF
Total LdUse and ShftVictim Line Capacitances = 0.0272*75 Lines = 2.0 pF
Total Reset Line Capacitance = 0.0176*75 Lines = 1.3 pF
Total ResetR Line Capacitance = 0.1536*1 Lines = 0.1536 pF
Total nCOut Line Capacitance = 0.0272*75 Lines = 2.0 pF
Total FrzVictim and nFrzVictim Line Capacitance = 0.0368*75 Lines = 2.8 pF
Total nAVct Line Capacitance = 0.0512*75 Lines = 3.8 pF
Appendix H: Capacitance of Shared Owner Control Lines
PWtInProgB Line Capacitance (per cell) C
80mx4 m metal2 wire (0.01)*80/100=0.008 pF
24 m2 gate capacitance (12 E-4)*24 m2=0.0288 pF
Total capacitance 0.0368 pF
nSetOw and nSetSh Line Capacitances (per cell) C
80mx4 m metal2 wire (0.01)*80/100=0.008 pF
24 m2 gate capacitance (12 E-4)*24 m2=0.0288 pF
Total capacitance 0.0368 pF
ClrOw and ClrSh Line Capacitances (per cell) C
80mx4 m metal2 wire (0.01)*80/100=0.008 pF
12 m2 gate capacitance (12 E-4)*12 m2=0.0144 pF
Total capacitance 0.0224 pF
nShOut and nOwOut Line Capacitances (per cell) C
80mx4 m metal2 wire (0.01)*80/100=0.008 pF
36 m2 N+ capacitance (1.5 E-4)*36 m2=0.0054 pF
30 m N+ sidewall capacitance (3 E-4)*30 m2=0.0090 pF
Total capacitance 0.0443 pF
nEnRS Line Capacitance (per cell) C
80 mx4 m metal2 wire (0.01)*80/100=0.008 pF
48 m2 gate capacitance (12 E-4)*48 m2=0.0576 pF
Total capacitance 0.0656 pF
EnRS Line Capacitance (per cell) C
80 mx4 m metal2 wire (0.01)*80/100=0.008 pF
128 m2 gate capacitance (12 E-4)*128m2=0.1536 pF
Total capacitance 0.1536 pF
Total PWtInProgB Line Capacitance = 0.0368*75Lines = 2.8 pF
Total nSetOw and nSetSh Line Capacitance = 0.0368*75Lines = 2.8 pF
Total ClrOw and ClrSh Line Capacitance = 0.0224*75Lines = 1.7 pF
Total nShOut and nOwOut Line Capacitance = 0.0391*75Lines = 2.9 pF
Total nEnRS Line Capacitance = 0.0656*75Lines = 4.9 pF
Total EnRS Line Capacitance = 0.1536*75Lines = 11.5 pF
Appendix I: Capacitance of Ram Interface Control Lines
ByteSelect Line Capacitance (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
32 m2 gate capacitance/cell * 64 cells (12 E-4)*32*64 pF=2.5 pF
Total capacitance 3.3 pF
SelBlkData/SelWdData Line Capacitance
s (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
32 m2 gate capacitance/cell * 256 cells (12 E-4)*24*256 m2=7.4 pF
Total capacitance 8.2 pF
WdSel Line Capacitance
s (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
24 m2 gate capacitance/cell * 32 cells (12 E-4)*24*32 m2=0.92 pF
Total capacitance 1.76 pF
LdRdLatch Line Capacitance (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
8 m2 gate capacitance/cell * 256 cells (12 E-4)*8*256=2.5 pF
Total capacitance 3.3 pF
nLdRdLatch Line Capacitance (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
16 m2 gate capacitance/cell * 256 cells (12 E-4)*16*256=5.0 pF
Total capacitance 5.8 pF
Prech Line Capacitance (total)
7mmx4m metal1 wire 0.12*7 mm=0.84 pF
60 m2 gate capacitance/cell * 256 cells (12 E-4)*60*256=18.43 pF
Total capacitance 19 pF
Appendix J: Capacitance of VCam and RCam Interface Control Lines
WtEnable/nWtEnable Line Capacitance
s (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
48 m2 gate capacitance/cell * 30 cells (12 E-4)*48*30 pF=1.7 pF
Total capacitance 1.8 pF
nPartMch Line Capacitance
s (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
32 m2 gate capacitance/cell * 30 cells (12 E-4)*32*30 m2=1.15 pF
Total capacitance 0.96 pF
DrBitLines Line Capacitance (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
98 m2 gate capacitance/cell * 30 cells (12 E-4)*98*30 m2=3.5 pF
Total capacitance 3.6 pF
nDrBitLines Line Capacitance
s (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
112 m2 gate capacitance/cell * 30 cells (12 E-4)*112*30 m2=4.0 pF
Total capacitance 4.12 pF
DrRdLatch Line Capacitance
s (total) [Upper bound]
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
120 m2 gate capacitance/cell * 22 cells (12 E-4)*120*22 m2=3.168 pF
Total capacitance 3.2 pF
LdRdLatch Line Capacitance (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
16 m2 gate capacitance/cell * 30 cells (12 E-4)*16*30=0.576 pF
Total capacitance 0.70 pF
nLdRdLatch Line Capacitance (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
32 m2 gate capacitance/cell * 30 cells (12 E-4)*32*30=1.15 pF
Total capacitance 1.3 pF
Prech Line Capacitance (total)
1mmx4m metal1 wire 0.12*1 mm=0.12 pF
240 m2 gate capacitance/cell * 30 cells (12 E-4)*240*30=8.64 pF
Total capacitance 8.8 pF
ClrVPV (ClrRPV) Line Capacitance (per cell)
80 mx4 m metal2 wire (0.01)*80/100=0.008 pF
16 m2 gate capacitance/cell * 75 cells (12 E-4)*16*75=0.0192 pF
Total capacitance 0.0272 pF
Capacitance for 75 cells 2.0 pF
Appendix K: Capacitance of Array Clock and nClock Lines
BigFF
96 m2 gate capacitance (Clock) (12 E-4)*96 pF=0.12 pF
96 m2 gate capacitance (nClock) (12 E-4)*96 pF=0.12 pF
VCamInterface
0.12pF/BigFF*3BigFF's/side*2sides 0.12*3*2=0.72 pF
RCamInterface
0.12pF/BigFF*3BigFF's/side*2sides 0.12*3*2=0.72 pF
RML23Interface
0.12pF/BigFF*4BigFF's/side*2sides 0.12*4*2=0.96 pF
Victim
0.07*numMemLines/side*2sides 0.07*75*2=10.5 pF
CSMuxInterface
0.12pF/BigFF*1BigFF's/side*2sides 0.12*1*2=0.24 pF
RML4Interface
0.12pF/BigFF*2BigFF's/side*2sides 0.12*4*2=0.48 pF
SORInterface
0.12pF/BigFF*4BigFF's/side*2sides 0.12*4*2=0.96 pF
Total Capacitance
Gate capacitance 14.5 pF
Wire capacitance 1.5 pF
Total 16 pF