1. Modify precharge connections in Cam and Ram interfaces.

Removed one stage of delay from xEnCamSel in CSMuxInterface and put it in RCamInterlockCtl which generates xEnCamSel. As a consequence, moved the generation of LdUse from VictimInterface to RCamInterlockCtl.

Removed the circuitry to generate ClrVPV from VCamInterface and put it in VCamInterlockCtl, where it belonged in the first place. This change makes the interface controls for RCam and VCam identical.

Removed circuitry for generating LdRML1 and ClampRM from RCamInterface and put it in RCamInterlockCtl.

1. Removed control circuitry from RamInterface and put it in RamInterlockCtl. The components removed were: the 8 flip-flops connected to xByteSel, xWdAdrs, xSelWdData; and the decoder for WdAdrs.

2. Took remaining RamInterfaceCtl circuitry and put it in SharedOwnerInterface.

Removed control circuitry from VCam and RCam Interfaces and put as much of it as would fit in VictimInterface. Moved the BigFF's computing nPartMch to RCamAMInterface and moved the inverters computing LdRdLatch and DrBitLines for VCam and RCam to RML1Interface and RCamAMInterface, respectively. Also moved the flop and nor combination feeding to the BigFF that computes DrBitLines to RCamInterlock and VCamInterlock.

Removed PCmd, PMode, PByteSel, and PFaultCode from PInterface.sch and put them in PInterfaceCtl where they belonged in the first place.

Made a boatload of small changes that I was too lazy to log.

The cache reached a major milestone today in that it executed the tests SmallCacheInner-PAll and SmallCacheInner-BAll both at transistor level and at behavioral level for each of the Array and the OutputSection. It is therefore time to merge in the version of JMF's SmallCacheArray and also make the cleanup changes Don has accumulated. Since these changes need to made extremely carefully, they will be logged below so if the simulation doesn't work anymore we have a handle on what's changed:

1. SmallCacheArray: ARM renamed to ARM3 in RCamAMInterface.

2. SmallCacheArray: BCycle2 renamed to RBycle2 throughout.

3. SmallCacheArray: BCycle3 renamed to RBycle3 throughout.

4. SmallCacheArray: BCycle4 renamed to RBycle4 throughout.

5. SmallCacheArray: In CamInterfaceCtl.sch, changed RdCam input to CCamPr, and added the input LdCamRL (the 3-input nand solution didn't work out for layout reasons).

6. SmallCacheArray: In Victim added nReset to base cells and left and right interfaces. In base cell, replaced nand2 by nand3 with nReset as the third input. In interface added inverter to generate nVR (logically nReset).

7. SmallCacheArray: Changed CK to Clock at top level of Array.sch.

8. SmallCacheArray: In FFWithEnAndnEn.sch, added buffer at output for safety.

9. SmallCacheArray: In FIFODataWtInterface.sch, added buffer at input for safety.

1. SmallCache: Edited SmallCacheInner to accommodate new Array.sch and BARData.icon.

2. SmallCache: Deleted Clock and nClock connections to Array.sch.

3. SmallCache: Deleted LdRML1 connection from Array.sch; LdRML1 changed to RBCycle2.

4. SmallCache: Removed 1/2 clock delay on enCamSelExt from RCamInterlockCtl.

5. SmallCache: Added buffer to generate CK from Clock at top level in SmallCacheInner.

6. SmallCache: Deleted PCmd from top level since there was only one occurrence.

7. SmallCache: Deleted PMode from PInterface and brought it out from PInterfaceCtl to Control.icon.

8. SmallCache: Deleted PByteSel from PInterface since there was only one occurrence.

9. SmallCache: Modified Control for BlockAssemblyRegister to use SS only parts.

1. SmallCacheArray: Added inverter to buffer BlkRdData and WdRdData. Doesn't change ifc.

2. Oracle Changes: