1. Check that ArrayVM, ArrayShOut, and ArrayRM are latched in such a way that they are valid for two cycles. This is to make it impossible for latches in PInterfaceCtl driven by PCycle1, PCycle2, etc. to glitch because of ArrayVM and ArrayShOut.

2. Provide a way to load the FIFO header from the input to the RBuf.

3. Provide a way to cancel an FBRqst in the FIFO when the Snooper says so.

4. In PInterfaceCtl LdPAdrs is not generated correctly in case of a fault. The problem is that a command in the following PhA will see a reject.

5. The cache needs to distinguish between BIO and IO. One way to do this is to not put the Id part of an IO address in the array but put it outside. Lets call this the IOITdMatcher. The signal that it produces is IOITdMatch.

6. Take care of Set and Clr owner from bus side.

7. Make BCtlSelWSData depend on CWSEq with a hardsire mux.

8. Optimize the bus side microprogram (factor common terms).

9. Make sure that in the SharedOwner interface layout, the pullup transistor is able to overcome the weak transistor in the latch.

10. Prepare streamlined victim cell for Lochner.

11. Think some more about SharedOwnerCell to see if it can be made smaller.

1. Add the pristine bit, which indicates that there has been no write into the cache from the processor side. The advantage of having this bit is that the IFU will never contend for its RAM with RBRqst's coming over the bus. Since RB's are the most frequent transactions, we've essentially eliminated RAM contention for the IFU cache