DIRECTORY Core, CoreCreate, CoreFlat, FSM, Ports, SCParms, Sisyph; SmallCacheLogic: CEDAR DEFINITIONS ~ BEGIN CellType : TYPE = Core.CellType; CellTypes: TYPE = LIST OF Core.CellType; CellTypeSpec: TYPE = SCParms.CellTypeSpec; Context: TYPE = Sisyph.Context; Level: TYPE = Ports.Level; LevelSequence: TYPE = Ports.LevelSequence; LevelSequenceRec: TYPE = Ports.LevelSequenceRec; LevelType: TYPE = Ports.LevelType; PA: TYPE = CoreCreate.PA; Port: TYPE = Ports.Port; Properties : TYPE = Core.Properties; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; Wires: TYPE = Core.Wires; WR: TYPE = CoreCreate.WR; SignalType: TYPE = {Input, Output, InputOutput, Power}; Signals: TYPE = REF SignalsRec; SignalsRec: TYPE = RECORD [ numSignals: NAT _ 0, signals: SEQUENCE size: NAT OF RECORD [ name: ROPE _ NIL, size: NAT _ 0, st: SignalType, l: Level _ X, ls: LevelSequence _ NIL, index: NAT _ Xs ] ]; Xs: NAT = LAST[NAT]; NumStackBits, NumPCBits: NAT; cacheStateValueA, cacheStateValueB, cacheStateValueC, cacheStateValueD, cacheStateValueE, cacheStateValueF, cacheStateValueG, cacheStateValueH, cacheStateValueI, cacheStateValueJ, cacheStateValueK, cacheStateValueL, cacheStateValueM, cacheStateValueN, cacheStateValueO: ROPE; transistor: CoreFlat.CutSet; SCacheHybrid: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; SCache: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; Inner: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; LeftCtl: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; DataPath: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; RightCtl: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; Array: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; ArrayGetState: PUBLIC PROC [] RETURNS [csv: ROPE]; ArrayPutState: PUBLIC PROC [csv: ROPE]; PmCodeFSM: PROC [usePC: BOOL _ TRUE, reg: FSM.RegisterType _ none, impl: ATOM _ $SC] RETURNS [ct: CellType]; PmCode: PROC [] RETURNS [ct: CellType]; Prech: PROC [cx: Context, ds: Ports.Drive] RETURNS [ct: CellType]; OutputSection: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; BCyclePipe: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; BlockAssemblyRegister: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; BWdWtPipe: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; SmallCache: PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType]; Declare: PROC [signals: Signals, name: ROPE, l: Level, st: SignalType] RETURNS [ix: NAT]; DeclareS: PROC [signals: Signals, name: ROPE, size: NAT, lc: CARD, st: SignalType] RETURNS [ix: NAT]; Create: PROC [roseClassName: ROPE, signals: Signals] RETURNS [ct: CellType]; GetPortIndices: PROC [signals: Signals, ct: CellType]; XInInputs: PROC [p: Port, s: Signals] RETURNS [BOOL _ FALSE]; OutputsToX: PROC [p: Port, s: Signals]; OutputsToDefault: PROC [p: Port, s: Signals]; CopyInputValues: PROC [s: Signals, p: Port]; CopySignals: PROC [to, from: Signals]; CopyLS: PROC [dest, source: LevelSequence, index: NAT _ 0]; XInLS: PROC [ls: LevelSequence] RETURNS [BOOL _ FALSE]; END. SmallCacheLogic.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Written by: Pradeep Sindhu, July 27, 1987 1:59:35 pm PDT Pradeep Sindhu, May 11, 1988 0:20:30 am PDT Don Curry June 10, 1988 1:23:40 pm PDT This interface provides create procs for cache subblocks that have procedural descriptions. It also contains low level utility procedures used in writing modules that define the subblocks. Standard Defs Type Defs Constants Public variables Create Procs for Cache Subblocks Utility Procs Used By Subblock Modules Κ/˜codešœ™Kšœ Οmœ1™