DIRECTORY Core, CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, SmallCacheLogic, SCParms, Sisyph; SmallCacheBlockAssemblyRegisterImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, SCParms, Sisyph EXPORTS SmallCacheLogic ~ BEGIN OPEN SmallCacheLogic; InternalState: TYPE = RECORD [ bar: LevelSequence, en: LevelSequence ]; State: TYPE = REF StateRec; StateRec: TYPE = RECORD [ bCycleAdrs: LevelSequence, master: InternalState, slave: InternalState ]; CycleIn, BCtlBlkWt5, BCycle0, BCycle1, BlkWtData, Clock: NAT; BlockAssemblyRegister: PUBLIC PROC [cts: CellTypeSpec, cx: Context] RETURNS [ct: CellType] = { public: Wire _ CoreCreate.WireList[LIST[CoreCreate.Seq["CycleIn", SCParms.numBitsPerCycle], CoreCreate.Seq["BlkWtData", SCParms.numBitsPerLine], "BCtlBlkWt5", "BCycle0", "BCycle1", "Clock"]]; SELECT cts FROM Schematic => ct _ Sisyph.ES["BlockAssemblyRegister.sch", cx]; Procedure => { ct _ CoreClasses.CreateUnspecified[public: public]; [] _ Rosemary.BindCellType[cellType: ct, roseClassName: myBlockAssRegName]; [] _ CoreFlat.CellTypeCutLabels[ct, "Logic"]; Ports.InitPorts[ct, ls, none, "CycleIn"]; Ports.InitPorts[ct, l, none, "BCtlBlkWt5", "BCycle0", "BCycle1", "Clock"]; Ports.InitPorts[ct, ls, drive, "BlkWtData"]; }; CoreFile => ERROR ENDCASE => ERROR }; Init: Rosemary.InitProc = { s: State; IF oldStateAny=NIL THEN { s _ NEW [StateRec]; s.bCycleAdrs _ NEW [LevelSequenceRec[SCParms.logNumCyclesPerLine]]; s.master.bar _ NEW [LevelSequenceRec[SCParms.numBitsPerLine]]; s.master.en _ NEW [LevelSequenceRec[SCParms.numCyclesPerLine]]; s.slave.bar _ NEW [LevelSequenceRec[SCParms.numBitsPerLine]]; s.slave.en _ NEW [LevelSequenceRec[SCParms.numCyclesPerLine]]; } ELSE s _ NARROW [oldStateAny, State]; Ports.SetLS[s.bCycleAdrs, X]; Ports.SetLS[s.master.bar, X]; Ports.SetLS[s.master.en, X]; Ports.SetLS[s.slave.bar, X]; Ports.SetLS[s.slave.en, X]; [CycleIn, BCtlBlkWt5, BCycle0, BCycle1, BlkWtData, Clock] _ Ports.PortIndexes[cellType.public, "CycleIn", "BCtlBlkWt5", "BCycle0", "BCycle1", "BlkWtData", "Clock"]; stateAny _ s; }; Simple: Rosemary.EvalProc = { s: State _ NARROW[stateAny]; IF NOT clockEval THEN SELECT p[Clock].l FROM L => { numEnablesHigh: NAT _ 0; FOR cycle: NAT IN [0..SCParms.numCyclesPerLine) DO IF p[BCycle0].l=H OR p[BCtlBlkWt5].l=H THEN s.master.en[cycle] _ L ELSE { prevCycle: INT; FOR i: NAT IN [0..SCParms.logNumCyclesPerLine) DO s.bCycleAdrs[i] _ p[CycleIn].ls[SCParms.numBitsPerCycle-SCParms.numWordsPerCycle*(SCParms.logNumWordsPerLine-i)+1]; ENDLOOP; prevCycle _ (cycle-1) MOD SCParms.numCyclesPerLine; IF prevCycle<0 THEN prevCycle _ SCParms.numCyclesPerLine-1; IF (p[BCycle1].l=H AND Ports.LSToC[s.bCycleAdrs]=cycle) OR s.slave.en[prevCycle]=H THEN s.master.en[cycle] _ H ELSE s.master.en[cycle] _ L }; SELECT s.slave.en[cycle] FROM H => { IF (numEnablesHigh _ numEnablesHigh+1) > 1 THEN ERROR; FOR i: NAT IN [0..SCParms.numBitsPerWord) DO s.master.bar[i*SCParms.numWordsPerLine+SCParms.numWordsPerCycle*cycle] _ p[CycleIn].ls[2*i]; s.master.bar[i*SCParms.numWordsPerLine+SCParms.numWordsPerCycle*cycle+1] _ p[CycleIn].ls[2*i+1] ENDLOOP; }; X => { FOR i: NAT IN [0..SCParms.numBitsPerWord) DO s.master.bar[i*SCParms.numWordsPerLine+SCParms.numWordsPerCycle*cycle] _ X; s.master.bar[i*SCParms.numWordsPerLine+SCParms.numWordsPerCycle*cycle+1] _ X ENDLOOP; }; ENDCASE ENDLOOP; }; H => { Ports.CopyLS[s.master.en, s.slave.en]; Ports.CopyLS[s.master.bar, s.slave.bar]; }; X => { Ports.SetLS[s.master.en, X]; Ports.SetLS[s.master.bar, X]; Ports.SetLS[s.slave.en, X]; Ports.SetLS[s.slave.bar, X]; }; ENDCASE => ERROR; Ports.CopyLS[s.slave.bar, p[BlkWtData].ls] }; myBlockAssRegName: ROPE = Rosemary.Register[roseClassName: "SmallCacheBlockAssemblyRegister", init: Init, evalSimple: Simple, scheduleIfClockEval: TRUE]; END. SmallCacheBlockAssemblyRegisterImpl.mesa Pradeep Sindhu April 26, 1988 12:51:28 pm PDT Paraminder Sahai September 24, 1987 0:27:17 am PDT Constants and Type Defs Signal Defs Public Procs Internal Procs Compute master.en[cycle] Compute master.bar[cycle] Ê ˜™(Icode™-K™2J™—šÏk ˜ Kšœi˜i—J™KšÑbln#œœ˜2KšœD˜KKšœ˜Kšœ œ˜headšÏl™šœœœ˜J˜J˜K˜—Kšœœœ ˜šœ œœ˜J˜Jšœ˜Jšœ˜Kšœ˜——šŸ ™ Kšœ8œ˜=K˜—šŸ ™ šžœœœ"œ˜^Kšœ#œ˜˜¿K˜šœ˜Kšœœ"˜=šœ˜Kšœ4˜4KšœK˜KKšœ-˜-Kšœ)˜)KšœJ˜JKšœ,˜,K˜—Kšœ ˜Kšœ˜——Kšœ˜—šŸ™šžœ˜Kšœ ˜ K˜šœ ˜šœ˜Kšœœ ˜Kšœœ0˜CKšœœ+˜>Kšœœ-˜?Kšœœ+˜=Kšœ œ-˜>K˜—Kšœœ˜%—K˜Kšœ˜K˜K˜K˜K˜K˜Kšœ¤˜¤K˜Kšœ ˜ Kšœ˜K˜—šžœ˜Kšœ œ ˜K˜š œœ œœ ˜,šœ˜Kšœœ˜šœœœ˜2K™šœœ˜&Kšœ˜šœ˜Kšœ œ˜šœœœ"˜1Kšœs˜sKšœ˜—Kšœœ˜3Kšœ œ(˜;K˜šœœ"œ˜RKšœ˜Kšœ˜—K˜—K˜—K™šœ˜˜Kšœ)œœ˜6šœœœ˜,Kšœ\˜\Kšœ_˜_Kšœ˜—K˜—˜šœœœ˜,KšœK˜KKšœL˜LKšœ˜—K˜—Kš˜—Kšœ˜—K˜—˜K˜&K˜(K˜—˜K˜K˜K˜K˜K˜—Kšœœ˜—K˜K˜*K˜—K˜—Kšœœ|œ˜™Kšœ˜J™—…—îÿ