SCLogic.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Written by: Pradeep Sindhu, July 27, 1987 1:59:35 pm PDT
Pradeep Sindhu, September 24, 1987 10:12:20 pm PDT
This interface provides create procs for cache subblocks that have procedural descriptions. It also contains low level utility procedures used in writing modules that define the subblocks.
DIRECTORY
Core, CoreCreate, Ports;
SCLogic: CEDAR DEFINITIONS
~ BEGIN
Standard Defs
CellType : TYPE = Core.CellType;
CellTypes: TYPE = LIST OF Core.CellType;
Level: TYPE = Ports.Level;
LevelSequence: TYPE = Ports.LevelSequence;
LevelSequenceRec: TYPE = Ports.LevelSequenceRec;
LevelType: TYPE = Ports.LevelType;
PA: TYPE = CoreCreate.PA;
Port: TYPE = Ports.Port;
Properties : TYPE = Core.Properties;
ROPE: TYPE = Core.ROPE;
Wire: TYPE = Core.Wire;
Wires: TYPE = Core.Wires;
WR: TYPE = CoreCreate.WR;
Type Defs
SignalType: TYPE = {Input, Output, InputOutput, Power};
Signals: TYPE = REF SignalsRec;
SignalsRec:
TYPE =
RECORD [
numSignals: NAT ← 0,
signals:
SEQUENCE size:
NAT
OF
RECORD [
name: ROPE ← NIL,
size: NAT ← 0,
st: SignalType,
l: Level ← X,
ls: LevelSequence ← NIL,
index: NAT ← Xs
]
];
Constants
Xs: NAT = LAST[NAT];
NumStackBits, NumPCBits: NAT;
Create Procs for Cache Subblocks
SCPmCode: PROC [] RETURNS [ct: CellType];
SCOutputSection: PROC [] RETURNS [ct: CellType];
SCArray: PROC [] RETURNS [ct: CellType];
SCBCyclePipe: PROC [] RETURNS [ct: CellType];
SCBlockAssemblyRegister: PROC [] RETURNS [ct: CellType];
SCBWdWtPipe: PROC [] RETURNS [ct: CellType];
Utility Procs Used By Subblock Modules
Declare: PROC [signals: Signals, name: ROPE, l: Level, st: SignalType] RETURNS [ix: NAT];
DeclareS: PROC [signals: Signals, name: ROPE, size: NAT, lc: CARD, st: SignalType] RETURNS [ix: NAT];
Create: PROC [roseClassName: ROPE, signals: Signals] RETURNS [ct: CellType];
XInInputs: PROC [p: Port, s: Signals] RETURNS [BOOL ← FALSE];
OutputsToX: PROC [p: Port, s: Signals];
OutputsToDefault: PROC [p: Port, s: Signals];
CopyInputValues: PROC [s: Signals, p: Port];
CopySignals: PROC [to, from: Signals];
CopyLS: PROC [dest, source: LevelSequence, index: NAT ← 0];
XInLS: PROC [ls: LevelSequence] RETURNS [BOOL ← FALSE];
END.