SCBCyclePipe.mesa
Pradeep Sindhu October 6, 1987 10:12:12 pm PDT
Paraminder Sahai September 24, 1987 0:28:32 am PDT
DIRECTORY
Core, CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, SCLogic, SCParms;
SCBCyclePipe: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, Ports, Rosemary, SCParms
EXPORTS SCLogic
~ BEGIN OPEN SCLogic;
Constants and Type Defs
NumBitsPerWord: NAT = SCParms.numBitsPerWord;
NumBitsPerCycle: NAT = SCParms.numBitsPerCycle;
LogNumWordsPerLine: NAT = SCParms.logNumWordsPerLine;
InternalState: TYPE = RECORD [
a, b, c, d: LevelSequence ← NIL
];
State: TYPE = REF StateRec;
StateRec: TYPE = RECORD [
master: InternalState,
slave: InternalState
];
Signal Defs
BCycle6, BCycle4, BCycle2, RAdrs, D, Q, BWdAdrs56, BCmd34, RplyShared34, BCmd2, Clock: NAT;
Public Procs
SCBCyclePipe : PUBLIC PROC [] RETURNS [ct: CellType] = {
public: Wire ← CoreCreate.WireList[LIST[CoreCreate.Seq["RAdrs",NumBitsPerWord],
CoreCreate.Seq["D",NumBitsPerCycle], CoreCreate.Seq["Q",NumBitsPerCycle], CoreCreate.Seq["BCmd2",5], CoreCreate.Seq["BCmd34",5], CoreCreate.Seq["BWdAdrs56",LogNumWordsPerLine], "BCycle6", "BCycle4", "BCycle2", "RplyShared34", "Clock"]];
ct ← CoreClasses.CreateUnspecified[public: public];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: bCyclePipeName];
[] ← CoreFlat.CellTypeCutLabels[ct, "Logic"];
Ports.InitPorts[ct, ls, none, "D"];
Ports.InitPorts[ct, l, none, "BCycle6", "BCycle4", "BCycle2", "Clock"];
Ports.InitPorts[ct, l, drive, "RplyShared34"];
Ports.InitPorts[ct, ls, drive, "RAdrs"];
Ports.InitPorts[ct, ls, drive, "BCmd2"];
Ports.InitPorts[ct, ls, drive, "BCmd34"];
Ports.InitPorts[ct, ls, drive, "BWdAdrs56"];
Ports.InitPorts[ct, ls, drive, "Q"]
};
Internal Procs
Init: Rosemary.InitProc = {
s: State;
IF oldStateAny=NIL
THEN {
s ← NEW [StateRec];
s.master.a ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.master.b ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.master.c ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.master.d ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.slave.a ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.slave.b ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.slave.c ← NEW[LevelSequenceRec[NumBitsPerCycle]];
s.slave.d ← NEW[LevelSequenceRec[NumBitsPerCycle]];
}
ELSE s ← NARROW[oldStateAny, State];
Ports.SetLS[s.master.a, X];
Ports.SetLS[s.master.b, X];
Ports.SetLS[s.master.c, X];
Ports.SetLS[s.master.d, X];
Ports.SetLS[s.slave.a, X];
Ports.SetLS[s.slave.b, X];
Ports.SetLS[s.slave.c, X];
Ports.SetLS[s.slave.d, X];
[BCycle6, BCycle4, BCycle2, RAdrs, D, Q, BWdAdrs56, BCmd34, RplyShared34, BCmd2, Clock ] ← Ports.PortIndexes[cellType.public, "BCycle6", "BCycle4", "BCycle2", "RAdrs", "D", "Q", "BWdAdrs56", "BCmd34", "RplyShared34", "BCmd2", "Clock" ];
stateAny ← s;
};
Simple: Rosemary.EvalProc = {
s: State ← NARROW[stateAny];
IF NOT clockEval THEN SELECT p[Clock].l FROM
L => {
Ports.CopyLS[p[D].ls, s.master.a];
IF p[BCycle2].l=H THEN Ports.CopyLS[s.slave.a, s.master.b];
IF p[BCycle4].l=H THEN Ports.CopyLS[s.slave.b, s.master.c];
IF p[BCycle6].l=H THEN Ports.CopyLS[s.slave.c, s.master.d];
};
H => {
Ports.CopyLS[s.master.a, s.slave.a];
Ports.CopyLS[s.master.b, s.slave.b];
Ports.CopyLS[s.master.c, s.slave.c];
Ports.CopyLS[s.master.d, s.slave.d];
};
X => {
Ports.SetLS[s.master.a, X];
Ports.SetLS[s.master.b, X];
Ports.SetLS[s.master.c, X];
Ports.SetLS[s.master.d, X];
Ports.SetLS[s.slave.a, X];
Ports.SetLS[s.slave.b, X];
Ports.SetLS[s.slave.c, X];
Ports.SetLS[s.slave.d, X];
};
ENDCASE => ERROR;
Ports.CopyLS[s.slave.d, p[Q].ls];
FOR i:NAT IN [0..NumBitsPerWord) DO
p[RAdrs].ls[i] ← s.slave.a[2*i+1];
ENDLOOP;
FOR i:NAT IN [0..4] DO
p[BCmd2].ls[i] ← s.slave.a[2*i];
p[BCmd34].ls[i] ← s.slave.b[2*i];
ENDLOOP;
p[RplyShared34].l ← s.slave.b[12];
FOR i:NAT IN [0..LogNumWordsPerLine) DO
p[BWdAdrs56].ls[i] ← s.slave.c[2*(NumBitsPerWord-LogNumWordsPerLine+i)+1]
ENDLOOP;
};
bCyclePipeName: ROPE = Rosemary.Register[roseClassName: "SCBCyclePipe", init: Init, evalSimple: Simple, scheduleIfClockEval: TRUE];
END.