DIRECTORY CoreCreate, CoreFlat, CoreProperties, Ports, Rosemary, RosemaryUser; SICAnalogSlice: CEDAR PROGRAM IMPORTS CoreFlat, Ports, Rosemary = BEGIN OPEN CoreCreate; magicValue: ARRAY [0..8) OF Ports.Level _ [L, H, L, L, H, L, L, H]; AnalogSliceName: ROPE = Rosemary.Register[roseClassName: "AnalogSliceSim", init: ADCInit, evalSimple: ADCSimple]; ADCCutSet: CoreFlat.CutSet = CoreFlat.CreateCutSet[ cellTypes: LIST[AnalogSliceName], labels: LIST ["LogicMacro", "Logic"]]; ADCPorts: TYPE = REF ADCPortsRec; ADCPortsRec: TYPE = RECORD[ Vdd, Gnd, AVdd, AGnd, VSub, Vbias0, RefHi, RefLo, AnIn, AnCtrl, test, s, ts, AGC, tComp, Comp, an, tAn, RefCk: Ports.Port _ NIL ]; ADCState: TYPE = REF ADCStateRec; ADCStateRec: TYPE = RECORD [ ports: ADCPorts _ NIL, currentState: {reset, adc} _ reset, stateNumber: CARDINAL _ 0, -- [0..8] recordState: Ports.LevelSequence _ NIL ]; ADCStateToMaxChars: RosemaryUser.StateToMaxCharsProc = { maxChars _ 1; }; stateNames: ARRAY [0..8] OF ROPE _ ["0", "1", "2", "3", "4", "5", "6", "7", "8"]; ADCStateToRope: RosemaryUser.StateToRopeProc = { asBits: PACKED ARRAY [0..16) OF BOOL _ ALL[FALSE]; index: CARDINAL; FOR bit: CARDINAL IN [0..4) DO asBits[bit+12] _ value[bit]=H; ENDLOOP; index _ LOOPHOLE[asBits]; rope _ stateNames[index]; }; ADCBind: PUBLIC PROC [public: Wire, p: Ports.Port] RETURNS [ports: ADCPorts] ~ { ports _ NEW[ADCPortsRec]; {OPEN ports; [Vdd, Gnd, AVdd, AGnd, VSub, Vbias0] _ Ports.BindPorts[public, p, "Vdd", "Gnd", "AVdd", "AGnd", "VSub", "Vbias0"]; [AnCtrl, test, s, ts, AGC, tComp] _ Ports.BindPorts[public, p, "AnCtrl", "test", "s", "ts", "AGC", "tComp"]; [Comp, an, tAn, RefCk] _ Ports.BindPorts[public, p, "Comp", "an", "tAn", "RefCk"]; }; }; ADCInit: Rosemary.InitProc = { state: ADCState _ NEW[ADCStateRec]; state.ports _ ADCBind[cellType.public, p]; {OPEN state.ports; Ports.PD[tComp, drive]; Ports.PD[Comp, drive]; }; state.currentState _ reset; state.recordState _ NEW[Ports.LevelSequenceRec[4]]; FOR i: NAT IN [0..4) DO state.recordState[i] _ X ENDLOOP; stateValue _ state.recordState; stateAny _ state; }; ADCSimple: Rosemary.EvalProc = { OPEN Ports; AllOnes: PROC [s: Port] RETURNS [BOOL] ~ { FOR i: NAT IN [0..8) DO IF GLS[s, i]#H THEN RETURN [FALSE]; ENDLOOP; RETURN [TRUE]; }; state: ADCState _ NARROW[stateAny]; {OPEN Ports, state, state.ports; Process: PROC [s, Comp: Port] ~ { SELECT TRUE FROM currentState=reset => { IF GLS[s, 0]=H AND GLS[s, 1]=L THEN { currentState _ adc; stateNumber _ 0; PL[Comp, magicValue[0]]} ELSE PL[Comp, L] }; currentState=adc AND stateNumber=7 => { IF AllOnes[s] THEN {currentState _ reset; PL[Comp, L]} ELSE PL[Comp, magicValue[7]]}; ENDCASE => { IF GLS[s, stateNumber+1]#H THEN PL[Comp, magicValue[stateNumber]] ELSE { stateNumber _ stateNumber+1; PL[Comp, magicValue[stateNumber]]; }}; }; Process[s, Comp]; { n: NAT _ IF currentState=reset THEN 8 ELSE stateNumber; asBits: PACKED ARRAY [0..16) OF BOOL _ LOOPHOLE[n]; FOR bit: NAT IN [0..4) DO state.recordState[bit] _ IF asBits[bit+12] THEN H ELSE L; ENDLOOP; stateValue _ recordState; }; Process[ts, tComp]; }}; END. ζSICAnalogSlice.mesa Copyright Σ 1988 by Xerox Corporation. All rights reserved. Last Edited by: Louis Monier August 16, 1988 12:09:28 pm PDT Last Edited by: RBruce August 11, 1988 5:24:18 pm PDT AnalogSlice PL[tComp, L]; ΚΥ– "cedar" style˜codešœ™Kšœ<™