I People
Time Q1 Q2 Q3 Q4
Chips (11) ->17
Boards (0) -> 4 -------> 7
Syst+Diag (1) -> 1 -------> 4 --------> 6
CAD (0) -> 2 -------> 4 --------> 5
Software (0) -> 1 -------> 2 --------> 6
Explanations :
Chips : 1 mngr + 2 * 6 StdCell Chips + 4 Cache
Boards : 1 CPU, 1 Mem, 3 IOB, 1 Back, 1 IPI
Syst+Diag : 1 mngr ,1 Chips, 1 Board, 2 Syst simul, 1 elctr
CAD : 3 chip, 1 board, 1 layout
Soft : 1 mngr,1 krnel, 3 driver, 1 map
Workstations
Chips designers : 16 Sun 4/110
Syst+Diag : 6 Sun 4/360
Board Designers : 7 Sun 4/110
CAD support : 5 Sun 4/110
Software : 6 Sun4/110
Servers 3 Sun4/360
CADTools
Cadence 4 (cache)
LSI 8 (Std Cells)
Valid 7 (Boards)
Verilog 20 (Simulation)
Synopsys 1 (Synthesis)
Test & lab equipment
III NRE
Chips :
Cell Dvlp 100 K
Arbiter 200 K
MemCntrl 200 K
IOB 200 K
IPI 200 K
MAP 200 K
BIC 100 K
CkGen 100 K
Cache 500 K
------------------------------
Total 1.8 M
Chip Package : 50 K
Boards :
Test 50 K
CPU 50 K
Mem 50 K
IOB 75 K
IPI 50 K
Back 50 K
------------------------------
Total 325 K
Chassis + Pwr 100 K
TOTAL 2.275 M
IV Prototype Cost