-- FirstDeliverables.tioga
-- Jean Gastinel January 10, 1989 8:10:10 am PST

Primary Objective Specifications :
Final Specification of the components  -> end february (target date)
DynaBus Specification  -> end January
DynaBus logical Spec   P. Sindhu
DynaBus electrical Spec B. Gunning
DynaBus Packaging   B. Gunning
Debug Bus     JM. Frailong
Chip Specification   -> end february
Arbiter      J. Hoel
Memory Controller   J. Gasbarro / F. Cerakis
Cache       P. Sindhu, JH Chang
Array Spec of Cache  M. Ross
IOBridge      JM. Frailong/ D. Basset
IPI        ?
Map Cache     M. Cekleov / B. Brougher
BIC + CK Gen    B. Gunning
------------------------------
Board specification    ->
Processor Board    
Memory Board    
IOBoard
IPI ?
BackPanel     
Architecture specification  ->
System Configurations  
Programming model   
SAS simulator    A. Kow/R. Lee
Software port specification ->
Issues to solve -> specialized small technical groups
Hiring, Processor choice, Packaging, CADTools, Xerox prototype, LSI logic,
 Nat Sem, Diagnostics, System configurations, IPI, IO...
First groups :
Documentation Port : L. Bland/ A. Killiam
Processor interface : J. Hung
CADTools : D. Curry/D. Basset
Packaging : B. Gunning
...