<> <<>> <<>> Basic Facts: 1. MByte/MIPS = 64(MI + MD/3) -- assumes 64 byte block 2. Block size = 32 or 64 bytes for good cache performance [from simulations] 3. Single chip cannot have > 400 pins 4. More than 64 drivers on the Bus side cause electrical and cooling problems 5. Single, 64 bit Dynabus is not sufficient, so either MULTI, or BIG BUS COMPARISON MULTI BIG BUS 2/4 buses 128/256 bits Pins ok/ok single chip ctl impossible increased number of pins for interchip communication may require more than one chip to design Pins/Board 160/320 150/290 Scalability same chipset 1-4 chipset hard to downgrade to lowend Bandwidth 464/928 366/512 (420/640 optimistic) MIPS 230/625 190/267 cache size limited by tag in 1 chip additional latency => low per pc MIPS Complexity constant 1->2->4 much higher complexity Redundancy 4->2->1 easy Single point of failure => no redundancy