SYSTEM CONFIGURATIONS
SYSTEM CONFIGURATIONS
SYSTEM CONFIGURATIONS
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System Configurations
J. Gastinel
Dragon-88-xx October 1988
© Copyright 1988 Xerox Corporation. All rights reserved.
Keywords: Dragon, Dynabus, VLSI;
Maintained by: Bland.pa
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
System Configurations
1.0 Description
The DynaBus and the previous DynaBus Chip Set allow a wide variety of computer implementations, depending of the targeted application for a given range of performance.
The next pictures present some computer configurations in using a 40 Mips processor (peak) and show the following applications :
1) MonoBord MonoProcessor (35 Mips)
2) MonoBoard with MaxiRay Module 1-4 Multiprocessor (35 -> 120 Mips)
3) MultiBoard with MaxiRay Module MonoBus 1-6 Multiprocessor (30 -> 150 Mips)
4) MultiBoard MultiBus Multiprocessor (60 -> 400 Mips)
5) MultiBoard MultiBus First level "Prime" Multiprocessor (200 -> 1000 Mips)
6) MultiBoard MonoBus 2nd level cache Multiprocessor (120 -> 300 Mips)
7) MultiBoard MultiBus 2nd level cache Multiprocessor ( > 1 Gips)
8) Evolution of the family
Monoboard MonoProcessor (35 Mips)
MonoBoard with MaxiRay Module
1-4 Multiprocessor (35 -> 120 Mips)
MultiBoard MonoBus with MaxiRay Module
1-6 Multiprocessor (30 -> 150 Mips)
MultiBoard MultiBus Multiprocessor (60 -> 400 Mips)
MultiBoard MultiBus Multiprocessor
First level "Prime" (200 -> 1000 Mips)
MultiBoard MonoBus 2nd level cache Multiprocessor (120 -> 300 Mips)
MultiBoard MultiBus 2nd level cache Multiprocessor ( > 1 Gips)