Dragon  System Architecture
February 1988
1
           BUS INTERFACE
           
           
           Common logical connection

<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
<< DynaBus Logical Interface>>
<<Bus Transactions>>
<<
>>
<<Read Block    RA,VRA    RA,D0,D1,D2,D3>>
<<Write Block    RA,D0,D1,D2,D3    RA,X>>
<<Flush Block    RA,D0,D1,D2,D3    RA,X>>
<<Write Single    RA,D            RA,D>>
<<CondWS    RA,D            RA,D,D,D,D>>
<<IORead    IOA,X            IOA,D>>
<<IOWrite    IOA,D            IOA,X>>
<<BIOW        IOA,D            IOA,X>>
<<Map        VA,X            RA,X>>
<<DeMap        RA,X            RA,X>>
<<Shared Memory Model

>>


<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>


· Each operation is atomic
· Operations are serialized
· Real Time ordering respected

Single-Level Operation



<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>

· Invariants
I1. > 1 cached copies => Shared is set in each
I2. At most one cache has Owner set
I3. Copy last written has Owner set
I4. Cached copies have identical values
Two-Level Operation

<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
Invariants



I1. Every copy in a cache is also in its parent
I2. The parent of a copy has ExistsBelow set
I3. >1 brother copies => Shared set in each
I4. The son of a Shared copy has Shared set
I5. The parent of an Owner copy has Owner set
I6. At most one brother has Owner set
I7. Copy last written by a processor has Owner set
I8. Shared copies have identical values
Functional Specifications: MemOps



· PRead        32 bit address, 32 bit data
· PWrite        32 bit address, 32 bit data
· PByteWrite        32 bit address, 32 bit data
4 write enable bits
any of 16 patterns allowed
· CWS            32 bit address, 64 bit data 


Functional Specifications: CWS


· CWS[addr, old, new] RETURNS [sample]= {
sample _ addr^;
IF sample=old THEN addr _ new
}
· Implemented in caches
· No bus traffic for private data
· No locks anywhere 
· Maximum possible overlap 

Functional Specifications: IO

· Single common IO address space
· Much like memory (ie.  hit/miss)
· Local locations (accessable via P or B)
CWSOld        (32)
CWSNew        (32)
AidReg            (32)
FaultCode        (32)
InterruptStatus        (32)
InterruptMask        (32)
Operating Mode    (32)

Functional Specifications: Mapping


· One address space at a time
· Specified by AidReg
· No data flush on space change
· Writing to AidReg clears all VPValid
· Demap[realPage]
Cache initiates DeMap transaction
On reply all caches match and ClrVPValid
· Aliasing avoided automatically
Match on RA before writing
Cache Block Diagram
<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
Speed - Hit Case



· Nominal 2 micron CMOS
·  Match ~ 10 ns
·  Read/Write ~ 10ns
·  => ~ 30ns on chip access time achievable
·  Current design hampered by Dragon PBus
·  Three possible fixes
Asynchronous Interface
Synchronous with line buffer
Cache in processor pipeline
Yield Issues



· Fully associative good for yield
·  Disable bad lines  (fusing/shifting in)
prevent virtual/real matches (force valid=0)
force use=1 (performance hack)
·  Everything else works  (frequent  failures)
>99% of transistors are in array


Conventional Display Architecture
<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
<<Local Bus Configuration>>
<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
<<Interim Solution>>
<<[Artwork node; type 'ArtworkInterpress on' to command tool]>>
<<>>