DynaBus System Overview 
November 1988
1
           DynaBus System Overview
           
                       



I    Introduction
II    DynaBus : a VLSI Bus 
III    DynaBus VLSI Chip Set
IV    Micro-Packaging
V    System Architectures
VI    Conclusions
Motivations
Foundations for building architectures  for a wide range of document processing machines 

 ·  controllers : Printer, Network, Scanners...
      
 ·  servers : Data base servers, Printers, Gateway
      
 ·  workstations : mid, high & very high end
     
 => high data bandwidth,  high data processing
         
         
For this variety,  for incrementality, for cost... 
 =>  Multiprocessor Architecture 

·  Follows a first generation of shared memory
    multiprocessor on conventional Bus.
    Currently implemented in a Xerox product.
      
·  new generation using more advanced concepts
    in the Bus & new technology : VLSI, packaging 
                     
           
Design Space
What kind of multiprocessor ? 
   loosely coupled / thigtly coupled / Highly parallel ?
   
     ·  Moderate number (<100) of nearly state of the art
         microprocessors the more thigtly coupled  possible
         => more MIPS/$,  more applications
  
What kind of programming Model ? 
     Message Passing  / Shared memory  ?
     
       ·  We'll choose Shared memory because more flexibility
What kind of communication ?
     Busses, Cross-bar, Hypercube ? 
     
         · For first level connection Busses are simpler 
            & more flexibility
  
  All solutions are difficult to implement until the technology exits for an economic implementation of the Memory System.
    
The DynaBus Technology solves this problem
Basic Technology


· DynaBus  VLSI BUS, MultiProc, High Bandwidth
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· VLSI Chip Set
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· Micro-Packaging
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II. The DynaBus : a VLSI Bus
New generation of Bus for VLSI

· Primarily an "on board" Bus for connecting VLSI
· Implement Cache coherency for Multiprocessor
· High Bandwidth
Primarily Characteristics 

· Packet switched for very high speed & flexibility
   => dissociation between data transport time 
    & memory access  time  => scalability
 
· Versatility in configurations
Implementation 
   
· Mathematical model and proof of coherence
· Bridges with industrial standards busses
· Multilevel Cache support
· Extension to non busses  communication
· Debug Bus for initialization and debugging
· Minimun number of wires for 64 bits Data path
· Bandwidth from 200  to more than 700 MByte/sec
DynaBus Configurations
 Mono-Board Computer
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 Multi-Board Computer
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 Multi-Board & Multi-Module Computer
<< >>
Multi DynaBus
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Multi-level DynaBus


<< [Artwork node; type 'Artwork on' to command tool] VLSI interface>>
VLSI Interface
VLSI  functions  = previous Board functions
VLSI interface = Connector
 
=> The DynaBus define a  standard VLSI interface, like Backpanel Busses define Board interface


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Bus Transactions
<<Only 13 transactions for all operations>>

Read Block    RA,VRA        RA,D0-D7
<<Write Block    RA,D0-D7        RA,X>>
<<Flush Block    RA,D0-D7        RA,X>>
<<Write Single    RA,D            RA,D>>
<<CondWS    RA,D0-D7        RA,D0-D7>>
<<CtlRead    IOA,X            IOA,D>>
<<CtlWrite    IOA,D            IOA,X>>
<<CtlReadBlock    RA,VRA        RA,D0-D7>>
<<CtlWriteBlock    RA,D0-D7        RA,X>>
<<Interrupt    IOA,D0-D7        IOA,X>>
<<Map        VA,X            RA,X>>
<<DeMap        RA,X            RA,X>>
<<KillBlock    RA,X            RA,X>>
III.  DynaBus VLSI Chip Set

Only Seven Chips for all the family 

    · Arbiter : distributed arbiter
    · Memory Controller : High performance with ECC
    · Cache : connected to the processor
    · IOB : Input-Output Bridge for Industrial Busses 
    · Display/Printer Chip :  Programmable format
    · Map Cache : for virtual memory
    · BIC : Bus interface Chip
   

   
IV.  MicroPackaging
DynaBus take account micropackaging evolution  flexible pipelining, good electrical interface.
For short cycles, lines must act as perfect transmission lines 
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Using  SMD and BiCMOS interface very good characteristics
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Next step is using MultiChip Hybrid module
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V.  System Architectures
Monoboard system

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Monoboard system with Module
 (100 Mips)
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MultiBoard Multiple Bus system
    (>400 Mips)
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MultiBoard system with Modules 
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Conclusions 
High Performance System Building Blocks 

 ·   VLSI  Bus =>  SPEED & PERFORMANCE
       High quality  & Robust multiprocessor Bus
 ·   VLSI Chip Set   => COST & SIMPLICITY
   only seven LSI for all the family 
 
Architecture for a Wide range of applications


Unique Open architecture to industrial standards  => EASY INTEGRATION
 · Microprocessor independant
 · Bridge with existing standard Busses
 · Multi-Operating system Compatiblility


Good candidate for standardization