Jean Gastinel October 25, 1988 8:16:18 pm PDT

Steve,

I have read in detail your BU organization proposal, and here are some suggestions both on the different parts and on the use of people.

The basic modifications are in the "Engineering system" part. It seems that the "Service CPU" can be included in the "Board design" part (it will be probably inside the IOBoard itself) same for the "backpanel" which includes a "clock generator board", and I really believe that the Diagnostics are part of the design of the boards... If we do so, the "Engineering system" becomes more "packaging design", and I propose to put it at the same level that "Chip design" and "Board design" which can now be called "System design".
That will have the advantage to have close relations between the three components : Chips, Boards & packaging which really need a lot of coupling.
With these small modifications, the result is that at the top Engineering level, we have a very clean two-components structure formed in one side by the Engineering hardware system level, and the Engineering Software on the other side.

So here what we get :

----------------------

Administration

...

Engineering Hardware System manager (board, chips, packaging + diagnostics)
(the deliverable is the hardware of the machine with diagnostics)

 CAD/SIM
 Chip design
 (deliverables are Chips + Test vectors + documentation of chips)
  Small Cache
  Map Cache
  IOBridge
  Memory Controller
  Clock Generator
  Arbiter
  Bus Interface Chip
  Graphics ?
  Test Chips
 System design
 (deliverables are boards + diagnostics + documentations of boards)
  DynaBus specifications
  CPU module
  Memory module
  IO module & service CPU
  Backpanel & Clock gen
  Global System simulation
  Diagnostics
 Packaging design & quality
 (deliverables are mechanical+ quality analysis + documentation)
  Mechanical & power
  Signal integrity
  Chip packaging technology
  Hardware ECO management
  
  
Engineering Software and release manager
(the deliverable is UNIX on our multiprocessor)

 System Software
  UNIX port
  IO Drivers and performance
  Service CPU
 Release and QA
  Integration and release
  Installation & configuration
  Configuration & Tuning
 Documentation
  User installation and configuration
  Phase plan documentation coordinator

Manufacturing

  ......

Marketing
 ......

Program management
 ......

Architecture & performance
 ......

----------------------------

Now about people, it seems that we can have advantage in using key Xerox people in managing critical sections, because they have currently the knowledge. Some of these sections can be co-managed with a Sun co-manager, and this solution has the advantage to allow a smooth transition with time. Here what we can propose :


Engineering System manager    ( J. Gastinel / Sun Strong Technical person)
  (the deliverable is the hardware of the machine with diagnostics)
  
 Chip design manager    (P. Sindhu / Sun person ?)
 (deliverables are Chips + Test vectors + documentation of chips)
 
  Small Cache      M. Ross + 2 or 3 Sun people + NatSem people
  Map Cache      L. Monier? + Sun person
  IOBridge       2 Sun Persons
  Memory Controller    Jim Gasbarro + Sun person
  Clock Generator     Ed Richley + Sun person
  Arbiter       D. Curry/Ed McCreight + Sun person
  Bus Interface Chip    Ed Richley + Sun person
  Graphics ?      J. Hoel + Sun persons... ?
  Test Chips      ?
  Chip Documentation   L. Bland + Sun person
 
 System design manager    (J. M. Frailong / Sun person ?)
 (deliverables are boards + diagnostics + documentations of boards)
 
  DynaBus specifications   AllOfUs + Sun person
  CPU module      ?
  Memory module     Jim Gasbarro + Sun person
  IO module & service CPU  ?
  Backpanel & Clock gen   B. Gunning/E. Richley + Sun person
  Global system simulation  ?
  Diagnostics      ?
  Board Documentation   L. Bland + Sun person  

 
 
 Packaging design & quality manager  ( JC Cuenod ?/ Sun person)
 (deliverables are mechanical+ quality analysis + documentation)
  Mechanical & power   M. Overton + Sun person
  Bus test & Signal integrity  B. Gunning + Sun person
  Chip packaging technology ?
  Hardware ECO management ?


That is a first try. I'll be happy to read your comments.

Sincerely,

Jean