Electronic System
1 March 1988
1
           Fast & Low cost  Electronic System
           
                       



I    Introduction
II    Bus studies 
III    VLSI Chip Set
IV    Packaging
V    System Architectures
VI    Future Directions & Conclusions
Motivations
Foundations for building architectures  for a wide range of document processing machines 

      ·  controllers : Printer, Network, Scanners...
      
      ·  servers : Data base servers, Printers, Gateway
      
      ·  workstations : mid, high & very high end
     
           => high data bandwidth 
     
Parallel processing architecture studies

      ·  Follows a first generation of shared memory
          multiprocessor on conventional Bus.
          Currently implemented in the Xenith project.
      
      ·  new generation using more advanced concepts
          in the Bus & new technology : VLSI, packaging 
           
      ·  Evolution & Succession of the Dragon Project
          
      ·  Compatible with Operating systems like Mach
          or SunOS phase3 & languages like Cedar
Basic Technology


· Communications studies : VLSI BUS
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· VLSI Chip Set
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· Packaging
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Global Architecture


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II. Bus studies
New generation of Bus for VLSI

· More than one order of magnitude in bandwidth
· Multiprocessor

Implementation 

· Multi-segment pipelined Bus
· Full coding and Data on 64 bits 
· Hardware data consistency
· Split-cycle for very high speed
· Support multi-Bank of memory
· Mathematical model and proof of coherence
· Bridges with industrial standards busses
· Extension to non busses  communication
· Debug Bus for initialization and debugging
· Bandwidth from 200 MByte/sec to 1GByte/sec
III.  VLSI Chip Set

Only seven Chips for all the family 

    · BIC : Bus interface Chip
    · Arbiter : distributed arbiter
    · Memory Controller : High performance with ECC
    · IOB : Input-Output Bridge
    · Display/Printer Chip :  Programmable format
    · Map Cache : for virtual memory
    · Cache : connected to the processor

IV.  Packaging
Principles 

· Design of a "Chip Carrier" containing  many Chips
· Intermediate level between Chips and Boards
· Perfect integration into our architecture
· Substrate in Silicon for experimentation
· Low to very low cost using large area process 

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Advantages for lots of applications 

· increase of speed
· gain in space
· solves power dissipation problems
· gain in cost 
V.  System Architectures

Monoboard system


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System Architectures (cont)
Example of 24 processors (400 Mips), 8 memory Banks and 2  IO Channels 
 
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MultiBoard Parallel system
with Hybrid Modules
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Results & Milestones

      
Chips Set :
      · 5 chips just return from fab, are under test
       (BIC, Arbiter, IOBridge, MemController, Simplex) 
       
      · 3 chips  will be sent 1-2 Q88
       (Cache, MAP Cache, Display/Printer)

       
Wire-Wrapped  Prototype :
       
       · 3Q 88      with 4  Sparcs 
                  (depends on the Cache)
                  
                  
High Speed Bus Prototype & Packaging :
       · 2Q 88
       
Transfer  of Research


Try to Standardize of the BUS

  ·  a VLSI BUS does not exist yet
   
   
   
Partnership 
  
  · with  Equipment maker like :  SUN
    
      · with  Semi-conductor companies :  Motorola,
      AMD...
       
         good chances because open architecture compatible with
    industrial standards : any microprocessor, any add-in boards &  
    possible multi-operating system... 
VI. Future Directions      

High Bandwidth is Crucial for  supporting  high performance VLSI operators

High speed printer , High speed network controller, Graphic controller, High speed disk controller, Compression Decompression of 
images...

· Specialized  operators connected to the Bus
        
· Increase the level of integration in one chip 
   Core processor + Cache + specialized operator
   
   
Future Directions  on parallelism 

Explore future parallel architecture in keeping this general model of   "Shared Memory with Caches" compatible with Mach, or SunOS 
phase 3 & Cedar

· MultiMegaByte Second level Caches

· Other topology to connect  specialized operators...
Conclusions 

Fast and Low cost electronic system
 
 ·   VLSI  Bus =>  SPEED & PERFORMANCE
order of magnitude in speed & multiprocessor oriented 
 ·   VLSI Chip Set   => COST & SIMPLICITY
only seven LSI for all the family, Chips replace boards 
 ·   Packaging   => COST, SIZE & PERFORMANCE
Advanced packaging used at the architecture level
 
 
 
Unique open architecture to industrial standards
        => EASY INTEGRATION
 · Any standard microprocessor
 · Bridge with existing standard busses
 · Standard Operating System for tightly coupled multiprocessor


Good candidate for standardization...