DynaBus : last issues DebugBus & Electrical Spec
 Next Tuesday (11/15th) documentation of
 modifications
 

Cache : Feasibility study progressing (due end Nov)
 Simulation give 14.6 ns worst case
 => need Sun market size

Packaging : OKI meeting for multi-chip module
 NS for flat pack. MaxiRay meeting (11/9)
  

Tools : Methodology study is starting
 => need Sun Cadence NDA
 => need starting to design a test chip

Global Architecture :
  Processor Choice & Connectivity study
  Multiple Busses & 2nd level caches issues
 => need Perf evaluation Maxiray non Harvard