DynaBus System Overview
December 1988
1
DynaBus System Overview
I Introduction
II DynaBus : a VLSI Bus
III DynaBus VLSI Chip Set
IV Micro-Packaging
V
Conclusions
Motivations
Foundations for building architectures for a wide range of document processing machines
· controllers : Printer, Network, Scanners...
· servers : Data base servers, Printers, Gateway
· workstations : mid, high & very high end
=> high data bandwidth, high data processing
For this variety, for incrementality, for cost...
=> Multiprocessor Architecture
· Follows a first generation of shared memory
multiprocessor on conventional Bus.
Currently implemented in a Xerox product.
· new generation using more advanced concepts
in the Bus & new technology : VLSI, packaging
Basic Technology
· DynaBus VLSI BUS, MultiProc, High Bandwidth
· VLSI Chip Set
[Artwork node; type 'Artwork on' to command tool]
· Micro-Packaging
II. The DynaBus : a VLSI Bus
New generation of Bus for VLSI
· Primarily an "on board" Bus for connecting VLSI
· Implement Cache coherency for Multiprocessor
· High Bandwidth
Primarily Characteristics
· Packet switched for very high speed & flexibility
=> dissociation between data transport time
& memory access time => scalability
· Versatility in configurations
Implementation
· Mathematical model and proof of coherence
· Bridges with industrial standards busses
· Multilevel Cache support
· Extension to non busses communication
· Debug Bus for initialization and debugging
· Minimun number of wires for 64 bits Data path
· Bandwidth from 200 to more than 700 MByte/sec
Multi-level DynaBus
[Artwork node; type 'Artwork on' to command tool] VLSI interface
VLSI Interface
VLSI functions = previous Board functions
VLSI interface = Connector
=> The DynaBus define a standard VLSI interface, like Backpanel Busses define Board interface
III. DynaBus VLSI Chip Set
Only Seven Chips for all the family
· Arbiter : distributed arbiter
· Memory Controller : High performance with ECC
· Cache : connected to the processor
· IOB : Input-Output Bridge for Industrial Busses
· Display/Printer Chip : Programmable format
· Map Cache : for virtual memory
· BIC : Bus interface Chip
IV. MicroPackaging
DynaBus take account micropackaging evolution flexible pipelining, good electrical interface.
For short cycles, lines must act as perfect transmission lines
[Artwork node; type 'Artwork on' to command tool]
Using SMD and BiCMOS interface very good characteristics
[Artwork node; type 'Artwork on' to command tool]
Next step is using MultiChip Hybrid module
[Artwork node; type 'Artwork on' to command tool]
Conclusions
High Performance System Building Blocks
· VLSI Bus => SPEED & PERFORMANCE
High quality & Robust multiprocessor Bus
· VLSI Chip Set => COST & SIMPLICITY
Architecture for a Wide range of applications
Unique Open architecture to industrial standards => EASY INTEGRATION
· Microprocessor independant
· Bridge with existing standard Busses
· Multi-Operating system Compatiblility
Good candidate for standardization