Dragon System Architecture
May 1988
1
DRAGON System Architecture

I Motivations
II The DynaBus
III VLSI Chip Set
IV Packaging
V Global Architecture
VI Future Directions
I. Motivations
Foundations for building architectures for a wide range of document processing machines

· controllers : Network, Scanners...

· servers : Data base servers, Printers, Gateway

· workstations : mid, high & very high end

=> high data bandwidth
Parallel processing architecture research

· Project started in 81

· Follows a first generation of shared memory
multiprocessor on conventional Bus.
Currently implemented in a Xerox product.

· new generation using more advanced concepts
& technology : VLSI, packaging

· Compatible with Operating systems like Mach
or SunOS phase3 & languages like Cedar
Dragon Technology
· Communications studies : VLSI BUS
[Artwork node; type 'Artwork on' to command tool]
· VLSI Chip Set
[Artwork node; type 'Artwork on' to command tool]
· Packaging
[Artwork node; type 'Artwork on' to command tool]
APPLICATIONS

Applications & markets

 · High end parallel computer


 · Desk-Top multiprocessor
 · High end Workstations

 · High end Printers servers
 · File and Data-bases servers

 · Add-in boards in standards platform
 · Industrial control
 · OEM multiprocessors


 · Chips set & packaging
II. The DynaBus
Very simple model for the programmer of a multiprocessor

All processors think they shared a unique memory.
Transparent Caches near each processor avoid bottleneck.
Implementation : VLSI BUS

· Multi-level Busses
· Well fitted for VLSI 64 bits
· Multiprocessors
· Hardware data consistency
· Split-cycle for very high speed
· Support multi-Bank of memory
· Mathematical model and proof of coherence
· Bridges with industrial standards busses
· Extension to non busses communication
· Bandwidth from 200 MByte/sec to 1GByte/sec
III. VLSI Chips set
Only seven Chips for all the family
· BIC : Bus interface Chip
· Arbiter : distributed arbiter
· Memory Controller : High performance with ECC
· IOB : Input-Output Bridge
· Display/Printer Chip : programmable
· Map Cache : for virtual memory
· Cache : connected the processor
IV. Packaging
Principles

· Design of a "Chip Carrier" containing many Chips
· Intermediate level between Chips and Boards
· Perfect integration into our architecture
· Substrate in Silicon using large area process of EIL
[Artwork node; type 'Artwork on' to command tool]
Advantages for lot of applications

· increase of speed
· gain in space
· solve power dissipation problems
· gain in cost
V Computer Architecture
[Artwork node; type 'Artwork on' to command tool]
VI Future Directions
This architecture is only at its beginning : Lot of Evolutions are expected : Progressive use of the Advanced packaging, & other topologies with multi-busses...
Future Directions on parallelism

Explore future parallel architecture in keeping this general model of
"Shared Memory with Caches"
Big opportunities with new operating systems like Mach, or SunOS phase3 which include this model of communication in the kernel, and languages like Cedar...
High Speed Bus is Crucial for supporting high performance VLSI operators

High speed vector processor, High speed network controller, graphic controller, High speed disk controller, Compression/Decompression of images...