1MemoryControllerSpec.tiogaCopyrightc1986byXeroxCorporation.Allrightsreserved.LastEditedby:GasbarroSeptember24,19864:09:13pmPDTJune87MemoryControllerBoardTheJune87DragonMemoryControllerboardsupportsfourbanksofrandomaccessmemory.Banksoperateindependentlysothattotalmemorybandwidthisroughlyproportionaltothenumberofbanksinthesystem.Eachbankwillinitiallyconsistof8MBytesofSingle-Error-Correct,Double-Error-Detect(SECDED)memoryusingSingleInlineMemoryModule(SIMM)mounted1MbitDRAMs.TherearenineRAMspermoduleandeightmodulesperbankforatotalof72RAMchips(64data+8ECC).Thecontrollerchipallowsforexpansionuptoamaximumof16banks,thoughthereisnospaceorpowerprovisionsinthecurrentpackagetoaccommodatethismuchmemory.Banksmustbeaddedinincrementsofpowersoftwo.ThecontrollerchipalsoprovidesextendedaddressingcapabilitytoprovideforfuturegenerationsofDRAMs.The1MbitSIMMscanbeupgradedwith4,16,or64Mbitparts.AcompletebankofmemoryconsistsoftheeightSIMMs,thecontrollerchip,threeAS-TTLdriversfortheRAMaddressandcontrollinesandpossiblyanadditionalchipprovidingtimingfortheRAM.Thesepartswilloccupytentofifteensquareinchesofboardspace.ChipDynaBusInterfaceThememorycontrollerrespondstothefollowingDynaBuscommands:ReadBlockRequest-readsfour64-bitwordsfrommemoryWriteBlockRequest-writesfour64-bitwordsfrommemoryWriteSingleRequest-reflectsreplyanddatatocachesbelowIOReadRequest-returnsfirstfailingaddressandsyndromeBroadcastIOWriteRequest-reflectsreplyanddatatocachesbelowThememorycontrollermaintainsaqueueofthoseDynabuscommandswhichitmustacton.Thesecommandsareexecutedintheorderinwhichtheywerereceived.Ifthequeueissofullthatanothercommandcouldcauseittooverflow,thememorycontrollernegotiateswiththearbitertostopincomingrequests.DataPathThedatapathofthememorycontrollerchip,illustratedintheblockdiagram[1],isfairlystraightforward.ThememorycontrollergeneratestheerrorcorrectingcheckbitsforeverywordthatisplacedontheDynabus.Inparalleltothisgeneration,thewordisdecodedbytheInputpg/Eq_, g]xr]q] (N*.d[x.$&*/1RsS g L gtI)Xa" )-371;=CH g $&p)=,a18:?& F] gj!'+y/@2@7r?E[D g'-.48= AzC gtu ' *-"04m6;><AAg g h!%(+G-Y.36 =@@}D? g  V"I&+h.0y26P8"<^ BD> gMw !>#'.q26*87C E[?D: g  #$(h-0/2>8|;=`?AC9" gu$)E+/-1e69 ?C7{ gNu#g&*-0i57z =@5 g^%'!$:(+M,1V59;?s/6 gu+ gMt()n #t%"'-3&)"&*.#):8 :#>'5+B.!&)!C$'*,70) 42!&*-0)= :$(+8.=/4<) $+%d)+a/4;@AiD g:5_"#&)+g/n2w5;=w?CEPf g $l%'[-X/5 ;C AD gup gt!)!U" (P+ 2@36i:7?ACv y g %%+#-x0 7A;=?C g4\ !&(k+ 2&48 9v>@CHTVm$12ControlFSMtodetermineifitisacommandintendedforthisbankandifso,howmanydatawordsfollow.OnlyvalidcommandanddatawordsareenteredintotheinputFIFO.WhenavalidcommandpropagatestothefrontoftheFIFOtheCommandDecodeFSMdetermineswhatRAMoperationshouldtakeplace,assemblesanyneededdataintheWriteBuffer,andinitiatestheRAMtimingsequence.WhentheRAMoperationhasfinishedandanyresulthasbeenlatchedintheReadbuffertheCommandDecodeFSMregistersareplyrequestwiththeRequestQueueFSM.Thisstatemachinekeepstrackofthenumberofpendingreplysandthenumberofcycleseachrequires.ItinturnissuesarequesttotheReplyControlFSMtonegotiatefortheDynabusandshiptheReplyCommandandData.InordertoimprovetheutilizationoftheRAM,theReadbufferisimplementedasdual-portedping-pongbuffer.Thus,whileonecommandiswaitingforit'sreplytobesent,anotherRAMoperationcanbeinitiatedandtheresultsstoredintheotherhalfoftheReadbuffer.TheBufferControlFSMhandleswhichportofthebuffershouldberead/writtennext.ControlMostofthecontrolcircuitryofthememorycontrollerisimplementedinthefivefinitestatemachines.Ofthesefive,twohavebeenimplementedwithhardwiredlogic.Theremainingthreewill(hopefully)beautomaticallygenerated.RAMTimingTheexactimplementationfortheRAMtiminggeneratorhasyettobedetermined.Therearethreepossiblecandidates:anexternaltiminggeneratorchip(Am2971),aninternalphase-lockedloopdelaycircuit,andaninternalsynchronousstatemachinegenerator.Therearemanyfactorsuponwhichtobasetheselectionfortheimplementationmethod,includingrisk,cost,numberofpins,boardspace,andaccesstime.Fortunatelythedecisioncanbedelayedforquitesometimewhileotheraspectsofthesystembecomemoreclear.DelayThemostimportanttimingspecforthememorycontrolleristheminimumdelayfromaReadBlockRequestonthebustothefirstwordofdatadelivered.Thisdelayisthesumofthefollowingdelays:fivepipelinestagesbetweenthebusandthetimethattheCommandDecodeFSMinitiatestheRAMcycle,thetotalRAMaccesstime(fromRAStothelastnibble),andtheoutputpipelinedelay.TheRAMaccesstimedependsonhowthetiminggeneratorisimplementedandonwhatspeedRAMswechoosetobuy.Upperandlowerlimitsare450-300ns.Theoutputpipedelayismoreinteresting.SincethedataisdeliveredfromtheRAMinthesamecyclicorderthatitmustbeshippedonthebusitispossibletobeginfillingtheoutputpipebeforetheendoftheRAMaccesstime.Thus,theoutputpipedelayisactuallynegativethreecycles.InadditiontothedatadelaythereistheconcernthatOwnerandSharedmustbereceivedbeforeRequestcanbeasserted.Thesesignalsarenotvaliduntilten(?)cyclesaftertheRequestcycle.AddedtothisistheminimumdelayfromRequesttoGrantasdeterminedbytheArbiter(3cycles?).Thetotaldelaythenis:MAX[(2cycles+300-450ns),13cycles]Assumingabuscycletimeof25nsandthefastestRAMaccesstime,theminimumRequesttodatadelaythenis350ns.Throughputpg/Et_/ g~<!c"(.0379; ==@CD] gyz"%(,/4 69M<AE[ gt |L!%c'>)-0O75)@DV gXj # ).279 <ADUC g. &\*1-/Z168=ADS gy !Y"%)*/e03>70<+?A,Q g#C#_*2,1Q3/68>.@ PM gk  (]* 1m7<@DhN gX>!m#-%0(~-17:r g=t:) q!$(,^247C8: C9$ gBT #Q)-48;?A7} g L"~$a)k 1M4q9 @D5 gFtY!#),.| 8o=D4. g\!$L(R,D 36 ;[=?D2 g^"$^&+90O3u/7 gt+) v#%(i- 4D58>>BlE*A g:D@ #T&0)+x. 5`8}<*=?BD( gOY{"H'),..0368& gC\U"5&N*-15u7Q9<AD%K gAM#(W+14+7:_?!E# g 7!a &$y&*,/4$6:l>@Q ! gZh  '+.+1J28BD U g!&(+j./1 6f8-<@*B gqAt!%0)O-4/4#7M;<A g"&*(+-35:e=AE#_ gn%).O03 6o9=A~D g=B #,)-I06(7<= E gH$!!$'U"&( /1)/!g$'=)-159;nA gVu g  vTVm$3AssumingminimumtimingforthebusandRAM,thethroughputforasinglebankofmemoryislimitedbytheabilitytocycletheRAM.Therearethreecyclesofoverheadinthestatemachineinadditiontothecycletimeandtheprechargetime.PrechargetimeforthefastestRAMsis100ns,sotheminimumcycletimefortheRAMisthreecyclesplus400nstodeliverfour64bitwords.Thethroughputthenis:4words/(3cycles+400ns)=8.5MWords/secondDebugInterfaceThesystem'sDBuswillbeusedtodownloadvariousregistersatsysteminitializationtime.TheMemoryandIOaddressspacewhichtheMemoryControlleroccupiesmustbeprogrammedbeforeanyaccessescanoccur.TheDBusisalsousedtoinitializeparametersspecifyingthesizeandspeedoftheRAMsusedandtherefreshrate.FeaturesYetToBeImplementedOwner,SharedFifoRAMTimingGeneratorDBusControllerReferences[1]Blockdiagram[Indigo]MemoryController>BlockDiagram.dale[2]Schematic(inprogress)[Indigo]MemoryController>MC.dalepg/Et_/)= #4%(+p/2s 91J37;;<=BD[ g\*!$(+Z-4P8?BWDZ9 g.H%)9,s.19596:W>bAqEeX g &*V N!%&(r,j.OS"k$P& uM gtJ) iG#8$+M057); CH g-Yc:!%(&- 4=9=> G5 gFt"R&'*F-z/ 4 ; BDiE g!{#(ws> g,Gt u; g/8S g=5 g< s.g g t+ )*2'< %N(gTVm$~ TIMESROMAN TIMESROMAN TIMESROMANYMATH TIMESROMAN HELVETICA j/A3[]<>Users>Gasbarro.pa>MC>MemoryControllerSpec.tioga'Wednesday, September 24, 1986 4:09 pm P