Create:
PROC
RETURNS [ct: CellType] = {
fsa: StateMachine;
CWSReq: Wire ← CoreOps.CreateWire[name: "CWSReq"];
OwnerAbort: Wire ← CoreOps.CreateWire[name: "OwnerAbort"];
FiveCycleReq: Wire ← CoreOps.CreateWire[name: "FiveCycleReq"];
TwoCycleReq: Wire ← CoreOps.CreateWire[name: "TwoCycleReq"];
RoomInPipe: Wire ← CoreOps.CreateWire[name: "RoomInPipe"];
ReplyIdle: Wire ← CoreOps.CreateWire[name: "ReplyIdle"];
NoDataForPipe: Wire ← CoreOps.CreateWire[name: "NoDataForPipe"];
SwRdPort: Wire ← CoreOps.CreateWire[name: "SwRdPort"];
SelRamBuf: Wire ← CoreOps.CreateWire[name: "SelRamBuf"];
AddressInPipe: Wire ← CoreOps.CreateWire[name: "AddressInPipe"];
OutBufRdAdd0: Wire ← CoreOps.CreateWire[name: "OutBufRdAdd0"];
OutBufRdAdd1: Wire ← CoreOps.CreateWire[name: "OutBufRdAdd1"];
public: Wire ← WireList[
LIST["Vdd", "Gnd", "Clock", "Reset",
CWSReq, OwnerAbort, FiveCycleReq, TwoCycleReq, RoomInPipe,
ReplyIdle, NoDataForPipe, SwRdPort, SelRamBuf, AddressInPipe, OutBufRdAdd0, OutBufRdAdd1]];
states: LIST OF ATOM ← LIST[$Idle];
states ← StateSeq[states, "RT", 2];
states ← StateSeq[states, "RF", 5];
states ← StateSeq[states, "RCWS", 5];
states ← StateSeq[states, "OA", 2];
fsa ← NewMachine[states];
Mealy[fsa, $Idle,
LIST[ReplyIdle, NoDataForPipe],
LIST [
[$Idle, Nor[And[FiveCycleReq, RoomInPipe], And[TwoCycleReq, RoomInPipe], OwnerAbort]],
[$RT0, And[TwoCycleReq, RoomInPipe]],
[$RF0, And[FiveCycleReq, Not[CWSReq], RoomInPipe]],
[$RCWS0, And[FiveCycleReq, CWSReq, RoomInPipe]],
[$OA0, OwnerAbort]
]];
Mealy[fsa, $RT0, LIST[AddressInPipe], LIST[[$RT0, Not[RoomInPipe]], [$RT1, RoomInPipe]]];
Mealy[fsa, $RT1,
LIST[OutBufRdAdd1, SwRdPort],
LIST [
[$RT1, Not[RoomInPipe]],
[$Idle, Nor[And[FiveCycleReq, RoomInPipe], And[TwoCycleReq, RoomInPipe], OwnerAbort]],
[$RT0, And[TwoCycleReq, RoomInPipe]],
[$RF0, And[FiveCycleReq, Not[CWSReq], RoomInPipe]],
[$RCWS0, And[FiveCycleReq, CWSReq, RoomInPipe]],
[$OA0, And[OwnerAbort]]
]];
Mealy[fsa, $RF0, LIST[AddressInPipe], LIST[[$RF0, Not[RoomInPipe]], [$RF1, RoomInPipe]]];
Mealy[fsa, $RF1, LIST[SelRamBuf], LIST[[$RF1, Not[RoomInPipe]], [$RF2, RoomInPipe]]];
Mealy[fsa, $RF2, LIST[SelRamBuf, OutBufRdAdd1], LIST[[$RF2, Not[RoomInPipe]], [$RF3, RoomInPipe]]];
Mealy[fsa, $RF3, LIST[SelRamBuf, OutBufRdAdd0], LIST[[$RF3, Not[RoomInPipe]], [$RF4, RoomInPipe]]];
Mealy[fsa, $RF4,
LIST[SelRamBuf, OutBufRdAdd0, OutBufRdAdd1, SwRdPort],
LIST [
[$RF4, Not[RoomInPipe]],
[$Idle, Nor[And[FiveCycleReq, RoomInPipe], And[TwoCycleReq, RoomInPipe], OwnerAbort]],
[$RT0, And[TwoCycleReq, RoomInPipe]],
[$RF0, And[FiveCycleReq, Not[CWSReq], RoomInPipe]],
[$RCWS0, And[FiveCycleReq, CWSReq, RoomInPipe]],
[$OA0, And[OwnerAbort]]
]];
Mealy[fsa, $RCWS0, LIST[AddressInPipe], LIST[[$RCWS0, Not[RoomInPipe]], [$RCWS1, RoomInPipe]]];
Mealy[fsa, $RCWS1, LIST[OutBufRdAdd1], LIST[[$RCWS1, Not[RoomInPipe]], [$RCWS2, RoomInPipe]]];
Mealy[fsa, $RCWS2, LIST[OutBufRdAdd1], LIST[[$RCWS2, Not[RoomInPipe]], [$RCWS3, RoomInPipe]]];
Mealy[fsa, $RCWS3, LIST[OutBufRdAdd1], LIST[[$RCWS3, Not[RoomInPipe]], [$RCWS4, RoomInPipe]]];
Mealy[fsa, $RCWS4,
LIST[OutBufRdAdd1, SwRdPort],
LIST [
[$RCWS4, Not[RoomInPipe]],
[$Idle, Nor[And[FiveCycleReq, RoomInPipe], And[TwoCycleReq, RoomInPipe], OwnerAbort]],
[$RT0, And[TwoCycleReq, RoomInPipe]],
[$RF0, And[FiveCycleReq, Not[CWSReq], RoomInPipe]],
[$RCWS0, And[FiveCycleReq, CWSReq, RoomInPipe]],
[$OA0, And[OwnerAbort]]
]];
Mealy[fsa, $OA0, LIST[SwRdPort, NoDataForPipe, AddressInPipe], LIST[[$OA1, true]]];
Mealy[fsa, $OA1,
LIST[NoDataForPipe],
LIST [
[$OA0, Not[RoomInPipe]],
[$Idle, Nor[And[FiveCycleReq, RoomInPipe], And[TwoCycleReq, RoomInPipe], OwnerAbort]],
[$RT0, And[TwoCycleReq, RoomInPipe]],
[$RF0, And[FiveCycleReq, Not[CWSReq], RoomInPipe]],
[$RCWS0, And[FiveCycleReq, CWSReq, RoomInPipe]],
[$OA0, And[OwnerAbort]]
]];
fsa.initialState ← FindState[fsa, $Idle];
ct ← StateMachineCell[public, fsa];
};