
    <<RAMControlFSM.mesa>>
        <<Copyright © 1986 by Xerox Corporation.  All rights reserved.>>
        <<Last Edited by: Gasbarro December 12, 1986 2:31:55 pm PST>>
        <<>>
    DIRECTORY  Core, Boole, CoreCreate, CoreOps, FiniteStateAutomata;

    RAMControlFSM: CEDAR PROGRAM
        IMPORTS Boole, CoreCreate, CoreOps, FiniteStateAutomata = 
        BEGIN OPEN Boole, CoreCreate, FiniteStateAutomata;

Create: PROC RETURNS [ct: CellType] = {
fsa: StateMachine;

StartA: Wire _ CoreOps.CreateWire[name: "StartA"];
Refresh: Wire _ CoreOps.CreateWire[name: "Refresh"];

SelWriteData0: Wire _ CoreOps.CreateWire[name: "SelWriteData0"];
SelWriteData1: Wire _ CoreOps.CreateWire[name: "SelWriteData1"];
RamBufWrAdd0: Wire _ CoreOps.CreateWire[name: "RamBufWrAdd0"];
RamBufWrAdd1: Wire _ CoreOps.CreateWire[name: "RamBufWrAdd1"];
RamBufWrite : Wire _ CoreOps.CreateWire[name: "RamBufWrite"];
SelColumnAdd: Wire _ CoreOps.CreateWire[name: "SelColumnAdd"];
nRAS: Wire _ CoreOps.CreateWire[name: "nRAS"];
nCAS: Wire _ CoreOps.CreateWire[name: "nCAS"];

    public: Wire _ WireList[LIST["Vdd", "Gnd", "Clock", "Reset",
        StartA, Refresh, SelWriteData0, SelWriteData1, RamBufWrAdd0, RamBufWrAdd1, RamBufWrite, SelColumnAdd, nRAS, nCAS]];

states: LIST OF ATOM _ LIST[$Idle];
states _ StateSeq[states, "Access", 10];
states _ StateSeq[states, "Refresh", 2];
    fsa _ NewMachine[states];

    Mealy[fsa, $Idle, LIST[nRAS, nCAS], 
        LIST [
            [$Idle, Not[StartA]],
            [$Access0, And[StartA, Not[Refresh]]],
            [$Refresh0, And[StartA, Refresh]]
            ]];

    Mealy[fsa, $Access0, LIST[nCAS], LIST [[$Access1, true]]];
    Mealy[fsa, $Access1, LIST[nCAS, SelColumnAdd], LIST [[$Access2, true]]];
    Mealy[fsa, $Access2, LIST[SelColumnAdd, RamBufWrite], LIST [[$Access3, true]]];
    Mealy[fsa, $Access3, LIST[nCAS], LIST [[$Access4, true]]];
    Mealy[fsa, $Access4, LIST[SelWriteData1, RamBufWrAdd1, RamBufWrite], LIST [[$Access5, true]]];
    Mealy[fsa, $Access5, LIST[nCAS, SelWriteData1, RamBufWrAdd1], LIST [[$Access6, true]]];
    Mealy[fsa, $Access6, LIST[SelWriteData0, RamBufWrAdd0, RamBufWrite], LIST [[$Access7, true]]];
    Mealy[fsa, $Access7, LIST[nCAS, SelWriteData0, RamBufWrAdd0], LIST [[$Access8, true]]];
    Mealy[fsa, $Access8, LIST[SelWriteData0, SelWriteData1, RamBufWrAdd0, RamBufWrAdd1, RamBufWrite], LIST [[$Access9, true]]];
    Mealy[fsa, $Access9, LIST[nRAS, nCAS, SelWriteData0, SelWriteData1, RamBufWrAdd0, RamBufWrAdd1], LIST [[$Idle, true]]];

    Mealy[fsa, $Refresh0, LIST[nRAS], LIST [[$Refresh1, true]]];
    Mealy[fsa, $Refresh1, NIL, LIST [[$Idle, true]]];

    fsa.initialState _ FindState[fsa, $Idle];
    ct _ StateMachineCell[public, fsa];
    };

    END.