Memory Controller August 4, 1988 1 The Memory Controller · Overview · Physical Layout · Dynabus Commands · Memory Address Space Partitioning · Programming Interface · Ram Timing Interface · Performance Calculations The Memory Controller · Interface between Dynabus and DRAM · Minimal amount of external circuitry · Up to 28 bit DRAM address · Nibble mode compressed timing · Flexible timing interface to DRAMs · Interleaving capability · Single-error correct, double-error detect · Dynabus common reflection point Dynabus memory system << [Artwork node; type 'Artwork on' to command tool] >> Pin Out · 80K transistors · 2 <<>> Block Diagram << [Artwork node; type 'Artwork on' to command tool] >> Physical Layout · Memory Controller chip · 72 DRAMs - 64 data - 8 ECC · Address buffer logic · Timing Logic << [Artwork node; type 'Artwork on' to command tool] >> Dynabus Commands <> Memory Address Space Partitioning · Block - Dynabus transport unit, 8 words · Bank - minimum memory increment banks can be interleaved 8 MBytes for 1 Mbit rams · Zone - set of Banks << [Artwork node; type 'Artwork on' to command tool] >> Memory Address Match << [Artwork node; type 'Artwork on' to command tool] >> · config. of Zone and Bank Address depends on - the number of banks in the zone - the address of the bank - the capacity of the DRAMs - the address of the zone Ram Address Selection << [Artwork node; type 'Artwork on' to command tool] >> · config. of Low Address depends only on the number of banks · config. of High Address depends on: - the number of banks in the zone - the capacity of the DRAMs · nibble mode addressing Memory Address Selection Example · configuration: four banks bank address 2 1 Mbit DRAMs Zone address 3 << [Artwork node; type 'Artwork on' to command tool] >> Programming · DBus Read Device Type and Version Number Register << [Artwork node; type 'Artwork on' to command tool] >> Syndrome, Error Status, and Address Register << [Artwork node; type 'Artwork on' to command tool] >> · DBus Write Device Number Register << [Artwork node; type 'Artwork on' to command tool] >> Programming (cont.) · IO Write RAM Timing, Miscellaneous Functions Register << [Artwork node; type 'Artwork on' to command tool] >> Zone Address Selection Register << [Artwork node; type 'Artwork on' to command tool] >> Memory Address, Bank Address Selection Reg. << [Artwork node; type 'Artwork on' to command tool] >> Clear Error Status Register << [Artwork node; type 'Artwork on' to command tool] >> Programming (cont.) · IO Read Error Address Register << [Artwork node; type 'Artwork on' to command tool] >> Error Status, Syndrome Register << [Artwork node; type 'Artwork on' to command tool] >> Ram Timing Interface · Memory Controller <-> DRAM Interface << [Artwork node; type 'Artwork on' to command tool] >> · Access timing << [Artwork node; type 'Artwork on' to command tool] >> · Refresh timing << [Artwork node; type 'Artwork on' to command tool] >> · Synchronization With The Memory Controller Performance · Two parallel delay paths owner delay + grant delay input delay + access delay << [Artwork node; type 'Artwork on' to command tool] >> Performance (cont.) · Three-level bus pipelined system - owner delay: 10 cycles - grant delay: 5 cycles · input delay: 4 cycles << [Artwork node; type 'Artwork on' to command tool] >> · access delay: ~300ns (current technology) << [Artwork node; type 'Artwork on' to command tool] >> << [Artwork node; type 'Artwork on' to command tool] >> Performance (cont.) · Delay Delay = MAX[input + access , owner + grant] Delay = MAX[4 cycles + 300ns , 15 cycles] Delay = MAX[400ns , 375ns] Delay = 400ns · Bandwidth BW = 8 words / (overhead cycles + access time + precharge time) BW = 8 words / (2 cycles + 300ns + 100ns) BW = 17.7 MW/sec = 71 MByte/sec · Throughput number of banks = memory cycle time / ReadBlock bus occupancy time number of banks = (overhead cycles + access time + precharge time) / 7 cycles number of banks = 2.6