<> <> <> <<>> DIRECTORY Atom, Core, CoreCreate, CoreOps, CoreProperties; MCWireIcons: CEDAR PROGRAM IMPORTS CoreCreate, CoreOps, CoreProperties ~ BEGIN dataBits: NAT = 64; correctBits: NAT = 8; width: NAT = 72; Wire: TYPE = Core.Wire; Side: TYPE = {Top, Bottom, Left, Right}; extractSchematic: BOOL _ TRUE; Corrector: PROC RETURNS [wire: Wire] ~ { sel: Wire _ CoreCreate.Seq["Sel", 18]; left: Wire _ CoreOps.CreateWires[width, "L"]; mid: Wire _ CoreCreate.Seq["M", width]; right: Wire _ CoreCreate.Seq["R", width]; vdd: Wire _ CoreOps.CreateWire[name: "Vdd"]; FOR i: NAT IN [0..correctBits) DO left[i] _ vdd; mid[i] _ vdd; right[i] _ vdd; ENDLOOP; FOR i: NAT IN [0..dataBits-1) DO left[i+correctBits] _ sel[17]; mid[i+correctBits] _ sel[15 - (i/8)]; right[i+correctBits] _ sel[7 - (i MOD 8)]; ENDLOOP; left[width-1] _ sel[16]; --the LSB of the data word maps to correction bit 62 mid[width-1] _ sel[15]; right[width-1] _ sel[6]; wire _ CoreCreate.Wires[sel, left, mid, right, vdd]; }; WirePosition: PROC [side: Side, index, size, inc, pos: NAT] RETURNS [wire: Wire] ~ { posProp: ATOM _ SELECT side FROM Top => $TopPosition, Bottom => $BottomPosition, Left => $LeftPosition, Right => $RightPosition, ENDCASE => NIL; IF size=0 THEN ERROR; IF inc=0 THEN ERROR; IF pos+1>inc THEN ERROR; IF size>1 THEN { wire _ CoreCreate.Seq[name: "X", size: size]; FOR i: NAT IN [0..size) DO CoreProperties.PutWireProp[wire[i], posProp, NEW[INT _ (index+i)*inc+pos]]; ENDLOOP; } ELSE wire _ CoreOps.CreateWire[name: "X", props: CoreProperties.Props[[posProp, NEW[INT _ index*inc+pos]]]]; }; END.