DRam.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Gasbarro September 22, 1986 3:01:18 pm PDT
Last Edited by: Gasbarro May 5, 1987 12:54:52 pm PDT
DRam: CEDAR DEFINITIONS
~ BEGIN
AddressBits: TYPE = (0..12];
AddressBit: TYPE = [FIRST[AddressBits]-1..LAST[AddressBits]-1];
Address: TYPE = LONG CARDINAL;
DataBits: TYPE = (0..16];
DataBit: TYPE = [FIRST[DataBits]-1..LAST[DataBits]-1];
Create:
PROC [a: AddressBits, d: DataBits]
RETURNS [ct: Core.CellType];
Creates a DRam with `a' address bits and 2**(2*a) words of storage, each containing 'd' data bits. Storage is implemented as a hash table so it's ok to ask for a big ram as long as you don't write into very many of the addresses.
SingleBitError:
PROC [state:
REF, a: Address, d: DataBit];
Inverts the d'th bit in storage at location 'a'
DoubleBitError:
PROC [state:
REF, a: Address, d0, d1: DataBit];
Inverts the d0'th and d1'th bits in storage at location 'a'
EnableUninitializedReads:
PROC [b:
BOOL];
When FALSE causes a SIGNAL when a location is read that has not been written. Proceeding from the SIGNAL will return 0; When TRUE causes the DRam to return zero without SIGNALing. This is a global parameter and affects all intances of DRam. If you set it to TRUE you had better know what you are doing...
END.