DIRECTORY MCDataPath, Core, CoreClasses, CoreOps, CMosB, DataPath, IO, Ports, Rope, Rosemary;

MCDataPathImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreOps, DataPath, IO, Ports, Rosemary
EXPORTS MCDataPath =

BEGIN

BusShort:	PUBLIC PROC[size: INT] RETURNS[wire: Core.Wire] = {
sub: Core.Wire _ CoreOps.CreateWires[0, "sw"];
wire _ CoreOps.CreateWires[size, "w"];
FOR i: INT IN [0..size) DO wire[i] _ sub ENDLOOP};

Trans: PUBLIC PROC[type: CoreClasses.TransistorType, length, width: INT]
RETURNS [cellType: Core.CellType] = {
name: IO.ROPE _ IO.PutFR["%g%gx%g",
IO.rope[CoreClasses.transistorTypeNames[type]],
IO.int[length],
IO.int[width]];
cellType _ CoreClasses.CreateTransistor[type, length, width, name]};

DPEdgeFFName: Rope.ROPE = Rosemary.Register[roseClassName: "DPEdgeFFSeq", init: DPEdgeFFSeqInit, evalSimple: DPEdgeFFSeqSimple, scheduleIfClockEval: TRUE];

DPEdgeFFSeqState: TYPE = REF DPEdgeFFSeqStateRec;
DPEdgeFFSeqStateRec: TYPE = RECORD [
in, out, ck: Ports.Port _ NIL,
master, slave: Ports.LevelSequence];

DPEdgeFFSeqInit: Rosemary.InitProc = {
state: DPEdgeFFSeqState;
IF oldStateAny=NIL THEN {
size: NAT _ p[Ports.PortIndex[cellType.public, "D"]].ls.size;
state _ NEW[DPEdgeFFSeqStateRec];
state.master _ NEW[Ports.LevelSequenceRec[size]];
state.slave _ NEW[Ports.LevelSequenceRec[size]];
} ELSE state _ NARROW[oldStateAny];
state.ck _ p[Ports.PortIndex[cellType.public, "CK"]];
state.in _ p[Ports.PortIndex[cellType.public, "D"]];
state.out _ p[Ports.PortIndex[cellType.public, "Q"]];
state.out.d _ drive;
Ports.SetLS[state.master, X];
Ports.SetLS[state.slave, X];
Ports.SetLS[state.out.ls, X];
stateAny _ state;
};

DPEdgeFFSeqSimple: Rosemary.EvalProc = {
state: DPEdgeFFSeqState _ NARROW[stateAny];
IF ~clockEval THEN {
SELECT state.ck.l FROM
L => Ports.CopyLS[from: state.in.ls, to: state.master];
H => Ports.CopyLS[from: state.master, to: state.slave];
ENDCASE => {
IF state.slave#state.master THEN Ports.SetLS[state.slave, X];
IF state.master#state.in.ls THEN Ports.SetLS[state.master, X];
};
};
Ports.CopyLS[from: state.slave, to: state.out.ls];
};

DPTSLatchName: Rope.ROPE = Rosemary.Register[roseClassName: "DPTSLatchSeq", init: DPTSLatchSeqInit, evalSimple: DPTSLatchSeqSimple, scheduleIfClockEval: TRUE];

DPTSLatchSeqState: TYPE = REF DPTSLatchSeqStateRec;
DPTSLatchSeqStateRec: TYPE = RECORD [
in, out, ck, en, dis: Ports.Port _ NIL,
slave: Ports.LevelSequence
];

DPTSLatchSeqInit: Rosemary.InitProc = {
state: DPTSLatchSeqState;
IF oldStateAny=NIL THEN {
size: NAT _ p[Ports.PortIndex[cellType.public, "D"]].ls.size;
state _ NEW[DPTSLatchSeqStateRec];
state.slave _ NEW[Ports.LevelSequenceRec[size]];
} ELSE state _ NARROW[oldStateAny];
state.ck _ p[Ports.PortIndex[cellType.public, "CK"]];
state.in _ p[Ports.PortIndex[cellType.public, "D"]];
state.out _ p[Ports.PortIndex[cellType.public, "Q"]];
state.en _ p[Ports.PortIndex[cellType.public, "en"]];
state.dis _ p[Ports.PortIndex[cellType.public, "dis"]];
state.out.d _ drive;
Ports.SetLS[state.out.ls, X];
Ports.SetLS[state.slave, X];
stateAny _ state;
};

DPTSLatchSeqSimple: Rosemary.EvalProc = {
state: DPTSLatchSeqState _ NARROW[stateAny];
IF ~clockEval THEN {IF state.ck.l=H THEN Ports.CopyLS[from: state.in.ls, to: state.slave]};
IF state.en.l=H AND state.dis.l=L THEN {
state.out.d _ drive;
Ports.CopyLS[from: state.slave, to: state.out.ls]} 
ELSE state.out.d _ none;
};

DPNOr3Name: Rope.ROPE = Rosemary.Register[roseClassName: "DPNOr3Seq", init: DPNOr3SeqInit, evalSimple: DPNOr3SeqSimple];

DPNOr3SeqState: TYPE = REF DPNOr3SeqStateRec;
DPNOr3SeqStateRec: TYPE = RECORD [
in0, in1, in2, out: Ports.Port];

DPNOr3SeqInit: Rosemary.InitProc = {
state: DPNOr3SeqState _ IF oldStateAny=NIL THEN NEW[DPNOr3SeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.in1 _ p[Ports.PortIndex[cellType.public, "in1"]];
state.in2 _ p[Ports.PortIndex[cellType.public, "in2"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPNOr3SeqSimple: Rosemary.EvalProc = {
state: DPNOr3SeqState _ NARROW[stateAny];
FOR index: NAT IN [0..state.in0.ls.size) DO
state.out.ls[index] _ SELECT TRUE FROM
state.in0.ls[index]=H OR state.in1.ls[index]=H OR state.in2.ls[index]=H => L,
state.in0.ls[index]=X OR state.in1.ls[index]=X OR state.in2.ls[index]=X => X,
ENDCASE => H;
ENDLOOP;
};

DPXOrName: Rope.ROPE = Rosemary.Register[roseClassName: "DPXOrSeq", init: DPXOrSeqInit, evalSimple: DPXOrSeqSimple];
DPXOrTopName: Rope.ROPE = Rosemary.Register[roseClassName: "DPXOrTopSeq", init: DPXOrSeqInit, evalSimple: DPXOrSeqSimple];
DPXOrBotName: Rope.ROPE =  Rosemary.Register[roseClassName: "DPXOrBotSeq", init: DPXOrSeqInit, evalSimple: DPXOrSeqSimple];

DPXOrSeqState: TYPE = REF DPXOrSeqStateRec;
DPXOrSeqStateRec: TYPE = RECORD [
in0, in1, out: Ports.Port];

DPXOrSeqInit: Rosemary.InitProc = {
state: DPXOrSeqState _ IF oldStateAny=NIL THEN NEW[DPXOrSeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.in1 _ p[Ports.PortIndex[cellType.public, "in1"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPXOrSeqSimple: Rosemary.EvalProc = {
state: DPXOrSeqState _ NARROW[stateAny];
FOR index: NAT IN [0..state.in0.ls.size) DO
state.out.ls[index] _ SELECT TRUE FROM
state.in0.ls[index]=X OR state.in1.ls[index]=X => X,
state.in0.ls[index] = state.in1.ls[index] => L,
ENDCASE => H;
ENDLOOP;
};

DPInvName: Rope.ROPE = Rosemary.Register[roseClassName: "DPInvSeq", init: DPInvSeqInit, evalSimple: DPInvSeqSimple];
DPInvDrName: Rope.ROPE = Rosemary.Register[roseClassName: "DPInvDrSeq", init: DPInvSeqInit, evalSimple: DPInvSeqSimple];
DPInvSeqState: TYPE = REF DPInvSeqStateRec;
DPInvSeqStateRec: TYPE = RECORD [
in, out: Ports.Port];

DPInvSeqInit: Rosemary.InitProc = {
state: DPInvSeqState _ IF oldStateAny=NIL THEN NEW[DPInvSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in0"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPInvSeqSimple: Rosemary.EvalProc = {
state: DPInvSeqState _ NARROW[stateAny];
Ports.NotLS[state.in.ls, state.out.ls];
};
DPTriDrInvName: Rope.ROPE = Rosemary.Register[roseClassName: "DPTriDrInvSeq", init: DPTriDrSeqInit, evalSimple: DPTriDrSeqSimple];
DPSCTriInvName: Rope.ROPE = Rosemary.Register[roseClassName: "DPSCTriInvSeq", init: DPTriDrSeqInit, evalSimple: DPTriDrSeqSimple];

DPTriDrSeqState: TYPE = REF DPTriDrSeqStateRec;
DPTriDrSeqStateRec: TYPE = RECORD [
in, out, en, dis: Ports.Port];

DPTriDrSeqInit: Rosemary.InitProc = {
state: DPTriDrSeqState _ IF oldStateAny=NIL THEN NEW[DPTriDrSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in"]];
state.out _ p[Ports.PortIndex[cellType.public, "out"]];
state.en _ p[Ports.PortIndex[cellType.public, "en"]];
state.dis _ p[Ports.PortIndex[cellType.public, "dis"]];
state.out.d _ drive;
stateAny _ state;
};

DPTriDrSeqSimple: Rosemary.EvalProc = {
state: DPTriDrSeqState _ NARROW[stateAny];
Ports.CopyLS[state.in.ls, state.out.ls];
state.out.d _ IF state.en.l=H AND state.dis.l=L THEN drive ELSE none;
};

DPBufName: Rope.ROPE = Rosemary.Register[roseClassName: "DPBufSeq", init: DPBufSeqInit, evalSimple: DPBufSeqSimple];
DPSCBufName: Rope.ROPE = Rosemary.Register[roseClassName: "DPSCBufSeq", init: DPBufSeqInit, evalSimple: DPBufSeqSimple];

DPBufSeqState: TYPE = REF DPBufSeqStateRec;
DPBufSeqStateRec: TYPE = RECORD [
in, out: Ports.Port];

DPBufSeqInit: Rosemary.InitProc = {
state: DPBufSeqState _ IF oldStateAny=NIL THEN NEW[DPBufSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in0"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPBufSeqSimple: Rosemary.EvalProc = {
state: DPBufSeqState _ NARROW[stateAny];
Ports.CopyLS[state.in.ls, state.out.ls];
};

DataPath.RegisterDataPathSpec["MC72", NEW[DataPath.DPSpecRec _ [
layDWidth:	72*	CMosB.lambda,
schDWidth:	9*	4*	CMosB.lambda,
layBusW:			8*	CMosB.lambda,
schBusW:			4*	CMosB.lambda,
metPitch:			8*	CMosB.lambda,
met2Pitch:		8*	CMosB.lambda,
leftTail:			4*	CMosB.lambda,	-- to center of 0th bus
rightTail:			4*	CMosB.lambda,	-- metPitch-leftTail
initialYSize:		3*	CMosB.lambda,	-- for channel use (=>top
gndBus:			0,
vddBus:			1,
pwrW:			5*	CMosB.lambda,
metW:				3*	CMosB.lambda,
met2W:			4*	CMosB.lambda,
polW:				2*	CMosB.lambda,
difW:				2*	CMosB.lambda,
pinSize:			2*	CMosB.lambda ]]];


END.

φMCDataPathImpl.mesa
Copyright c 1985 by Xerox Corporation.  All rights reserved.
Don Curry, November 11, 1987 1:36:42 am PST

EXPORTS
DPEdgeFF
DPTSLatch
DPNOr3
DPXOr, DPXOrTop, DPXOrBot
DPInv, DPInvDr
DPTriDrInv, DPSCTriInv
DPBuf, DPSCBuf

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