DIRECTORY Core, CoreFlat, CoreOps, Ports, PW, Rope, Rosemary, RosemaryUser, Sisyph; InterruptRequestTest: CEDAR PROGRAM IMPORTS CoreOps, Ports, PW, Rosemary, RosemaryUser, Sisyph = BEGIN InterruptTestProc: RosemaryUser.TestProc = { CycleInterruptLogic: PROC = { Step: TYPE = [0..8); XLevel: ARRAY Step OF Ports.Level _ [L, L, L, H, H, H, H, H]; YLevel: ARRAY Step OF Ports.Level _ [L, L, H, L, H, H, H, H]; --X.Y is an adder input with sequence [L, L, L, L, H, H, H, H] SILevel: ARRAY Step OF Ports.Level _ [L, L, H, H, L, L, H, H]; --other adder input CILevel: ARRAY Step OF Ports.Level _ [L, H, L, H, L, H, L, H]; SOLevel: ARRAY Step OF Ports.Level _ [L, H, H, L, H, L, L, H]; COLevel: ARRAY Step OF Ports.Level _ [L, L, L, H, L, H, H, H]; FOR step: Step IN Step DO p[XBit].l _ XLevel[step]; p[YBit].l _ YLevel[step]; p[ProdIn].l _ SILevel[step]; p[CarryIn].l _ CILevel[step]; p[ProdOut].l _ SOLevel[step]; p[CarryOut].l _ COLevel[step]; Eval[]; ENDLOOP; }; --CycleInterruptLogic p[XBit].l _ p[YBit].l _ p[ProdIn].l _ p[ProdOut].l _ p[CarryIn].l _ p[CarryOut].l _ L; CycleInterruptLogic[]; }; --InterruptTestProc viewerName: Rope.ROPE = "Interrupt Request Logic"; testee: Rope.ROPE = "IntrptRequestLatch.sch"; designName: Rope.ROPE = "///Users/gunther.pa/chips/IOPInterruptController"; ct: Core.CellType _ Sisyph.ExtractSchematicByName[testee, Sisyph.Create[PW.OpenDesign[designName]]]; Vdd: NAT = CoreOps.GetWireIndex[ct.public, "Vdd"]; Gnd: NAT = CoreOps.GetWireIndex[ct.public, "Gnd"]; XBit: NAT = CoreOps.GetWireIndex[ct.public, "XBit"]; YBit: NAT = CoreOps.GetWireIndex[ct.public, "YBit"]; CarryIn: NAT = CoreOps.GetWireIndex[ct.public, "CarryIn"]; ProdIn: NAT = CoreOps.GetWireIndex[ct.public, "ProdIn"]; ProdOut: NAT = CoreOps.GetWireIndex[ct.public, "ProdOut"]; CarryOut: NAT = CoreOps.GetWireIndex[ct.public, "CarryOut"]; ProdFeedthru: NAT = CoreOps.GetWireIndex[ct.public, "ProdFeedthru"]; [] _ Rosemary.SetFixedWire[ct.public[Vdd], H]; [] _ Rosemary.SetFixedWire[ct.public[Gnd], L]; FOR i: NAT IN [0..ct.public.size) DO [] _ Ports.InitPort[wire: ct.public[i]]; ENDLOOP; [] _ Ports.InitTesterDrive[wire: ct.public[XBit], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[YBit], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[CarryIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ProdIn], initDrive: force]; [] _ Ports.InitTesterDrive[wire: ct.public[ProdOut], initDrive: expect]; [] _ Ports.InitTesterDrive[wire: ct.public[CarryOut], initDrive: expect]; [] _ RosemaryUser.TestProcedureViewer[cellType: ct, testButtons: LIST["Interrupt Request Test"], name: viewerName, displayWires: LIST[NEW[CoreFlat.FlatWireRec _ [path: CoreFlat.NullPath, wire: ct.public]]], flatten: TRUE ]; END. φInterruptRequestTest.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Created by Neil Gunther, August 8, 1986 11:08:45 am PDT Last Edited by: Neil Gunther August 8, 1986 2:48:44 pm PDT -- Construct Truth Table Simulation ΚΑ˜™Icodešœ Οmœ1™˜VJšœ˜Kšœ’‘˜K˜—Kšœžœ˜5Kšœžœ˜.Kšœžœ6˜KK˜KšœΟbœJ˜dKšœžœ*˜2Kšœžœ*˜2Kšœžœ+˜4Kšœžœ+˜4Kšœ žœ.˜:Kšœžœ-˜8Kšœ žœ.˜:Kšœ žœ/˜