DRAGON I/O SUBSYSTEM
DRAGON I/O SUBSYSTEM
DRAGON I/O SUBSYSTEM
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
IOS: The Dragon I/O Subsystem
Design Overview and Data Sheets
Neil Gunther
© Copyright 1986 Xerox Corporation. All rights reserved.
Abstract: This document describes the basic architecture of the Dragon I/O subsystem (IOS) for the for the so-called "June87" machine. It contains an overview of the system, a complete description of the hardware design, and a description of the various I/O controllers.
Keywords: AMD, AT, Boot, Chipset, Communications, Counter, Debug, Disk, DMA, ESDI, Ethernet, Expansion, Floppy, IBM, Intel, Interrupt, IO, IOB, IOS, June87, Keyboard, Map, Microprocessor, Mouse, Multibus, Disk, RAM, ROM, RS232C, SloBus, SCSI, ST506, Subsystem, TeleDebug, Timer, VME
FileName: [Indigo]<Dragon>IOSubsystem>IOSubsystemDoc.tioga, .interpress
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
Dragon Project - For Internal Xerox Use Only
Contents
1. Board Overview
2. SloBus
3. Local Memory and Control
4. Arbitration
5. I/O Bridge
6. AT Microcomputer
7. Dedicated Ethernet Controller
8. Dedicated Disk Controller
9. Serial Communications Controller
10. Keyboard Controller
11. Teledebug Interface
12. AT Expansion Unit
13. Miscellaneous Components
Appendix A. Schematics for the IO Subsystem
Appendix B. Bibliography of Commercial Data Sheets
ChangeLog
1. Board Overview
The Dragon I/O subsystem (IOS) provides the following main functions. Control of all the external Dragon peripherals which are not attached directly to the Dragon Memory Bus. Control of the Dragon system during power-up and initialization. together with the booting function. Control of the diagnostics of the Dragon hardware. Capability of attaching optional commercial devices to the Dragon via a standard commercial bus extension.
1.1 Functionality
The Dragon requires 3
primary tasks to be performed by devices external to the main multi-processor system.
1. Initialization (including disk-boot capability) of the Dragon system and peripheral interfaces.
2. Medium and Low Speed I/O transactions for the Dragon system including those between a dedicated disk, an ethernet, and the keyboard.
3. Debug and Diagnostic facility.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Fig. X IOS Functional Blocks
1.2 Implementaton
The main bus on the I/O subsystem is called the SloBus. The I/O subsystem is controlled primarily by the IOP, a custom VLSI processor. Activity on the SloBus is handled by the SloArbiter. All SloBus arbitration is performed in cooperation with the 80186. With the exception of the display controller, all the I/O controllers interface to the SloBus. These devices include an Ethernet controller, an integrated hard/floppy disk controller, the expansion bus controller and serial devices, viz., the SCC, keyboard and, teledebugging interface.
The architecture of the subsystem falls into two pieces about the SloBus; the backplane section, where the IOP chip and the hard disk controller have connections to the Dragon Memory Bus, and the external section, where the remaining peripheral controllers on the SloBus are linked to their respective cable connectors.
2. SloBus
The SloBus provides the common communication backbone for the IO subsystem.
2.1 Functionality
The SloBus is an extended variant of the IBM PC-AT bus. It is composed of separate data and address lines, control lines, eight interrupt lines and ten arbitration lines. The major devices resident on the SloBus are 16-bit data path and have either 24- or 32-bit byte addressing.
2.2 Implementation
The SloBus comprises 34 lines of address, 16 data lines, 10 lines for control signals, an 8 line interrupt bus, and 10 discrete signals for SloBus arbitration. The SloBus propagates the 8MHz I/O system clock derived from the 80286.
Although the SloBus supports several Intel devices, the bus has non-multiplexed data and addressing because supporting devices which can act as multiplexed masters and slaves on the same bus introduces additional complications into the interface logic. This point is salient for the IOB, which can act both as SloBus master and slave and which already must demultiplex the Dragon Memory Bus. Several devices on the SloBus, most notably the IOB, the integrated disk controller and the expansion unit, are already non-multiplexed devices.
Address Bus
SA33-SA0
(
System Address Lines)
These lines are superset of the 20 lines, SA0-SA19, available on the standard AT I/O bus.
SA0-SA33 are gated onto the bus when BALE is asserted high; latched on the falling edge of BALE.
LA23-LA17
(
Unlatched Address Lines)
Valid when BALE is asserted. They are not latched during IO controller cycles and therefore are not valid for the whole cycle. Their purpose is to provide memory decodes for 16-bit, 1-wait state, memory cycles.
Data Bus
SD15-SD8 (System Data Lines)
SD7-SD0
(
System Data Lines)
Support for byte-wide devices is provide by having them use SD0-SD7 when communicating with the master and having the controller multiplex the high order byte into the low order byte.
Control Signals
BALE
(
Buffer Address Latch Enable)
Indicates a valid DMA address when used with AEN. BALE is forced active high during DMA cycles.
MEMCS16
(
16-bit Memory Device)
Indicates to the system that the present data transfer is a 16-bit, 1 wait-state, memory cycle.
It must be derived from the decoding of LA bus. Asserted low.
IOCS16
(
16-bit I/O Device)
Indicates to the system that the present data transfer is a 16-bit, 1 wait-state, I/O cycle.
It is derived from a decoding of SA bus. Asserted low.
-IOCHCK
(
IO Transfer Error Condition)
Provides parity information IO devices. This signal is asserted low and indicates a non-recoverable system error.
IOCHRDY
(
IO
Channel Ready)
Pulled low by IO device to lengthen IO or memory cycle. This signal should not be held low for more than 2.5 microseconds.
AEN
(
Address Enable)
Used by the DMA device to decouple other IO devices from the DMA channel. When asserted high, the DMA device has control of the AddressBus, DataBus Read/Write command lines.
SBHE
(
System Byte High Enable)
Indicates transfer of data on the high byte of the SD bus. Asserted high.
CLK
(
System Clock)
The system clock runs at half the frequency of the processor clock.
OSC
(Output)
The AT IO bus supplies a 14.32 MHz clock. This clock is not synchronized with the AT system clock.
OWS
(
Zero Wait State Condition)
This signal informs the 80286 that it can complete the present bus cycle without the insertion of additional wait states. Asserted low.
-MEMW
(
Write 1MB of System Memory )
Active on all memory write cycles. Address the first 1 MB of memory.
-MEMR
(
Read 1MB of System Memory )
Active on all memory read cycles. Address the first 1 MB of memory.
-SMEMW
(
Write
16MB of System Memory )
Address the first 16 MB of memory.
-SMEMR
(
Read
16MB of System Memory )
Address the first 16 MB of memory.
-IOW
(
I/O Write)
Instructs the IO device to read data from the SD bus. Asserted low.
-IOR
(
I/O Read)
Instructs the IO device to drive its data onto the SD bus. Asserted low.
RESETDRV
(
Reset Peripherals)
Used to reset or initialize the system. Asserted high.
Interrupts
IRQ (
Interrupt Request)
High priority
IRQ9(highest)-12
IRQ13 (not available for IO devices)
IRQ14-15
Low priority
IRQ3-7(lowest)
IRQ8 (used for real-time clock)
DMA Signals
DRQ
(
DMA Request)
Asynchronous channel requests used by IO devices to gain DMA service.
7 DMA channels; DRQ0 has highest priority; DRQ7 has lowest.
-DACK
(
DMA Acknowledge)
Used to acknowledge DMA requests.
TC (
Terminal Count )
Used to notify the currently selected peripheral that the present DMA cycle should be the last cycle for this data block.
-MASTER
Used with the ReqDMABus line to gain control of the system.
-REFRESH
3. Local Memory and Control
32KBytes of local EPROM and 128KBytes of RAM are provided.
3.1 Functionality
The local RAM will contain the buffer descriptors for the Ethernet controller (64KB max.) thereby avoiding long access times via the IOBridge. The EPROM will contain the initial boot code, and a simple monitor to allow debugging operations.
3.2 Implementation
The local RAM will be implemented as SIPS.
Address and IO space ranges.
4. Arbitration
Bus arbitration is performed by the AT processor.
4.1 Functionality
4.2 Implementation
5. I/O Bridge (IOB)
A semi-custom chip, called the IOBridge, is required to interface the SloBus, with the high speed system bus, the Dragon Memory Bus, and to handle a few specific functions that have no other place in the system.
The current truth about the IOB is contained in [Indigo]<Dragon>IOP>IOPDoc.tioga, interpress.
5.1 Functionality
The IOBridge is mostly a bridge between two buses having different protocols and speeds. The following types of transactions are supported.
a) Memory Read/Write from the SloBus: converted to Dragon Memory Bus BlockRead/BlockWrite through a cache for blocking/deblocking.
b) I/O Read/Write from the SloBus: access to internal IOBridge registers.
c) I/O Read/Write from the Dragon Memory Bus: converted to SloBus read/writes through a FIFO (the SloBus allows only one transaction at a time). SloBus memory reads, memory writes, I/O reads, I/O writes are supported. Dragon Memory Bus I/O transactions also allow access to internal IOP registers.
d) BlockReadReplies/BlockWriteReplies/WriteSingleReplies from the Dragon Memory Bus are used by the cache mechanism both as results of its actions in case of misses and also to do the snooping.
The IOBridge also contains the DBus controller, which is accessible only from the SloBus via the Song teledebug interface.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Fig. X IOBridge
5.2 Implementation
The IOBridge is built using a standard cell design in 2 mm CMOS technology and consists largely of a modified Dragon cache, bus translation and interrupt control logic.
6. AT Microcomputer
The IOS contains a resident microprocessor which is a master mode only device.
6.1 Functionality
The role of the local microprocessor is to provide initialization of the Dragon system and its peripherals and exercise control during teledebugging. In addition, the 80286 and its attendant AT controller chipset, will handle the MSDOS peripheral drivers.
6.2 Implementation
The physical implementation of the boot microprocessor is the Intel 80286. The microprocessor forms an integral part of the resident AT microcomputer. The AT microcomputer is based on a commercial six piece chipset comprising a system controller, a memory controller, a DMA controller and appropriate bus drivers and buffers.
7. Dedicated Ethernet Controller
The Ethernet controller manages the tasks of transmitting and receiving encoded data frames over a local area network. The Ethernet controller complies with the IEEE 802.3 10Base5 LAN Standard.
7.1 Functionality
a) The Data Link Controller manages network frame transmission and reception. In addition, it manages the network link by monitoring the presence and quality of activity on the media and taking appropriate action. The data link controller parameters are programmable.
The main functions of the this controller are: executing commands from the IOP and receiving serial data from the Serial Interface. These two essential functions are handled by two separate logical units within the Data Link Controller. They are the Command Unit (CU), which logically executes the action commands from the IOP, and the Receive Unit (RU), which logically receives and stores frames.
b) The Serial Interface performs Manchester encoding/decoding of the outbound/inbound serial data to provide the 10 MHz transmit and the recovered receive clock to the data link controller, and to provide the differential pair drive capability to the transceiver drop cable.
7.2 Implementation
The physical implementation of the Ethernet controller comprises two commercial VLSI chips. An Intel 82586 integrated data link controller, a SEEQ 8023A integrated serial interface, and a terminating resistor network.
NOTE: Although Intel makes the 82501 as a compatible Ethernet serial interface chip, it was not selected because it does not provide the correct wave shaping on the end of transmit waveform in 802.3 mode. As a consequence, TTL transceivers would turn on at the end of the packet.
8. Dedicated Disk Controller
The integrated disk controller provides the capability for transactions with any combination of up to four floppy and hard disk drives.
8.1 Functionality
ST506 drives can accomodate up to approximately 100 MB of storage. Newer ESDI drives can accomodate up to approximately 750 MB of storage.
8.2 Implementation
The Am 9580A supports any combination of up to four floppy and ST506 hard disk drives. The plug compatible Am 9590 supports ESDI in addition.
9. Serial Communications Controller
The Intel 8274 MPSC provides up to 9600 baud DTE and DCE lines.
9.1 Functionality
Something goes here.
9.2 Implementation
The Intel 8274 MPSC provides up to 9600 baud DTE and DCE lines.
The Z8530 SCC can accomodate up to 19.2 KBaud.
10. Keyboard Controller
All paragraphs in a Dragon document have the format body, except for paragraphs that continue after an equation or an in-line figure. These have the format block. All headings have the format head. Chapters should begin on an odd-numbered page, so a pageBreak node should be placed just prior to the chapter.
A node which defines the running head can be inserted nested under the chapter heading. It has the node property Mark with value centerRectoHeader. The TSetter understands this to be a header definition and diverts the text for later assembly during page layout. All paragraphs in a blue-and-white have the format body.
10.1 Functionality
Something goes here.
10.2 Implementation
Something goes here.
11. Teledebug Interface
A 20 pin socket is provided to allow connection to the Xerox standard "Song Board".
11.1 Functionality
The Telebedug interface provides capability for shifting processor state in and out via the DBus.
11.2 Implementation
Debugging operations are controlled by the 80186.
12. AT Expansion Unit
An ExpansionUnit facilitates the Dragon acting as a master on a wide variety of external option boards.
12.1 Functionality
The SloBus ExpansionUnit extends a buffered version of the SloBus to a connector at the edge of the IOS board and also converts the SloBus signals into a 62-pin IMB-PC connector. Only one of these extensions can be jumper selected to be electrically active on the IOS SloBus.
Note on Multibus Applications: To connect the Dragon IOS to a Multibus subsystem it is necssary to construct a Multibus interface board which accepts the buffered SloBus signals. Since the SloBus is essentially a demultiplexed 80186 bus, it is a straightforward matter to build the Multibus interface from an Intel 8288 Multibus Controller and an Intel 8289 Multibus Arbitration unit, all residing on a Multibus form factor board.
The maximum load placed on either of these extended buses should not exceed 2 LSTTL loads.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Fig. X AT Expansion Unit
12.2 Implementation
Something goes here.
13. Miscellaneous Components
Something goes here. Maybe??
13.1 MOSART Integrated Modem
Something goes here. Maybe??
13.2 VETO: A Remote Power Up Controller
Something goes here. Maybe??
13.3 DES: Data Encryption
Data encryption hardware is not part of the June87 IOS.
Appendix A. Schematics for the IOS
[Indigo]<Dragon>IOSubsystem>IOSubsystem.dale
Appendix B. Bibliography of IOS Commercial Components
Ethernet
Microcommunications Handbook,
Intel Corporation 1986
Chapter 2 provides details of the chip's functionality and control.
Chapter 3 provides programming information.
Chapter 5 contains application notes.
Chapter 8, p. 27ff. Data sheet for the 80586.
Microprocessors
Microsystems Components Handbook
- Microprocessors Volume 1,
Intel Corporation 1986
Chapter 3, p.52ff. Data sheet for the 80186.
Introduction to the 80386, including the 80386 Data Sheet, Intel Corporation 1986
Disks
MOS Microprocessors and Peripherals,
Advanced Micro Devices 1985
Chapter 2, p. 520ff. Data sheet for the Am9580.
Draft: Am9580A Data Sheet, 2/13/1986
Serial Communications
MOS Microprocessors and Peripherals,
Advanced Micro Devices 1985
Chapter 2, p. 147ff. Data sheet for the Z8530.
Chapter 2, p. 147ff. Data sheet for the Z8536.
Microcommunications Handbook,
Intel Corporation 1986
Chapter 9, p. 46ff. Data sheet for the 8247.
Xerox 6085 Workstation
Dove IOP Board Technical Reference Manual, Xerox Corporation, Nov. 1985
Dove IOP Board Appendix D: Representative Schematics, Xerox Corporation, Mar. 1986
Dove IOP Board Etch Schematics, Xerox Corporation, May 1986
ChangeLog
Created by Neil Gunther, September 5, 1986 6:45:22 pm PDT
Last edited by Neil Gunther, November 10, 1986 2:46:53 pm PST
Modified documentation for the PC-AT implementation.