Current status of the IOBridge - Very late compared to initial plan: PC interface incorrectly specified Pin count problem Specification modifications - Current status: IOBus interface being redesigned: Master complete, being tested Slave not finished DynaBus interface correct PBus interface designed, not tested Application schematic complete (update needed) - Planning: Not ready for a run before 1 month min. New IOBus specs - PC/AT bus now understood - PC bus extended to 32-bits addressing (hack) - Address mapping supported (2 maps!): 64K in [0..1M) mapped by 4K pages 14M in [1M..15M) mapped by 1M pages - Back-to-back cycles for 32-bit access - Full complement of byte-swapping methods: byte, INT16, INT32 orders - Estimated round-trip for PC access: DynaBus -> IOBus : 7 DynaBus CK IOBus: min. 4 PCLK+4 PCLK/16 bits IOBus -> DynaBus: 3 DynaBus CK --> + 2ms for a 32-bit transfer IOBridge pinout - Very close to 300-pin PGA limit: PGA allows 268 signal pins - IOBridge pins: DynaBus: 139/143 DBus: 10 (8 if slave only) PBus: 44/47 IOBus: 62 ----------------------- Total: 255/262 - Very tight fit - Pad-frame implementation may reveal topological problems DBus status - DBus now asynchronous with DynaBus: Allows clock tuning through DBus Almost no change in chip design (hidden in standard DBus interface) Allows non-DynaBus synchronous scan-paths - Multiple DBus scan-path per chip (8 max): Allows more flexibility 1 path for chip ID 1 path for clock tuning 1 path for DynaBus-clocked signals path(s) for other clocks - Negative aspects: DFreeze now asynchronous -> synchronous system start problematic Adds one pin to all chips (8 pins for slave DBus interface) - New DBus document to be released soon Κ–"slides" style˜title˜blockšœ%˜%L˜"L˜L˜—˜˜!L˜L˜—L˜L˜#L˜.—˜ L˜'——˜L˜L˜.˜&L˜!L˜#—L˜'˜+LšœΟkœœ˜—˜%L˜L˜!L˜LšœΟgœ˜——˜˜"L˜—˜L˜L˜L˜ L˜ L˜L˜—L˜L˜:—˜ ˜%L˜ L˜CL˜)—˜+L˜L˜L˜L˜"L˜—˜L˜@L˜;—L˜'——…—²½