0 1 1 1 00000000 | X X XXXXXXXX XXXXXXXX XXXXXXXX -- First reset 1 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check FCkOut is reset 0 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check RefClock is ineffective 1 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check RefClock is ineffective 0 0 1 0 01234567 | 0 0 00000000 XXXXXXXX XXXXXXXX -- Tmr1 _ 01234567 1 0 0 1 89ABCDEF | 0 0 00000000 01234567 XXXXXXXX -- Tmr2 _ 89ABCDEF, check Tmr1 0 0 1 0 FFFFFFFE | 0 0 00000000 01234567 89ABCDEF -- Tmr1 _ FFFFFFFE, check Tmr2 1 0 0 1 01234567 | 0 0 00000000 FFFFFFFE 89ABCDEF -- Tmr2 _ 01234567, check Tmr1 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ A, check Tmr2 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz _ F 1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- SCk1MHz _ 1 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- counters +_1 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ 9 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ A 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz _ F 1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 0 0 0 0 XXXXXXXX | 1 0 00000001 FFFFFFFF 01234568 -- SCk1MHz _ 1 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- counters +_1 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ 9 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ A 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz _ F 1 0 0 1 FFFFFFFE | 0 0 00000002 00000000 01234569 0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 FFFFFFFE -- SCk1MHz _ 1 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- counters +_1 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ 9 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ A 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz _ F 1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE 0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- SCk1MHz _ 1 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- counters +_1 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ 9 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ A 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz _ F 1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF 0 0 0 0 XXXXXXXX | 0 1 00000004 00000002 FFFFFFFF -- SCk1MHz _ 1 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- counters +_1 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ 9 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ A 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ B 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ C 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ D 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ E 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz _ F 1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- SCk1MHz _ 1 . \IOBTimingRegs.oracle Jean-Marc Frailong April 21, 1987 6:39:40 pm PDT This test file assumes that the prescaler counter has been set up to divide by 8 so as to reduce the length of the test... Outputs: RefClock (0), Reset (0), WTmr1 (0), WTmr2 (0), DIn (32) Inputs: Tmr1Int (0), Tmr2Int (0), FCkOut (32), Tmr1Out (32), Tmr2Out (32) RefClock Reset WTmr1 WTmr2 DIn | Tmr1Int Tmr2Int FCkOut Tmr1Out Tmr2Out -- Comment Reset sequence, pre-fill RefClock pipeline Check that the other timers do get written into correctly and test the first step of FCk One step of all counters, Tmr1Int gets raised One step of all counters, reload Tmr2 just before it gets incremented One step of all counters, Tmr2 is not updated One step of all counters, Tmr2 is updated this time and creates an interrupt One step of all counters, nothing happens ΚΆ˜™Icode™0—J˜J™z™J™7J™—™J™A—J™Jš(ΠftΟfžžžžžžžžžžžžžžžžœΟcΠctŸ ™hJ™šœ*™*JšžžžœŸ˜@JšžžžœŸ˜JJšžžžœŸ ˜RJšžžžœŸ ˜RJ˜—™XJšžžžœŸ˜DJšžžžœŸ˜PJšžžžœŸ˜PJš žžžœŸ ΠcfŸ ˜PJšžžžœŸ˜HJšžžž˜1JšžžžœŸ ˜