1 00000000 0 0 0 0 | XXXXXXXX XXXXXXXX XXXXXXXX X -- Unknown state 1 00000000 0 0 0 0 | XXXXXXXX 00000000 XXXXXXXX 0 -- Unknown state 1 00000000 0 0 0 0 | 00000000 00000000 XXXXXXXX 0 -- Reason is not reset 0 00000000 0 0 0 0 | 00000000 00000000 XXXXXXXX 0 -- Rescind Reset and check 0 12345678 3 0 0 0 | 00000000 00000000 XXXXXXXX 0 -- Write Reason 0 00000000 0 0 0 0 | XXXXXXXX 00000000 12340000 0 -- results in partial write only 0 00000000 0 1 0 0 | 00000000 00000000 12340000 0 -- Setup INT 0 00000000 0 0 0 0 | 00000000 00000000 12340000 0 0 00000000 0 1 0 0 | 80000000 00000000 12340000 0 0 00000000 0 1 0 0 | 00000000 00000000 12340000 0 -- Check 2 cycles delay 0 00000000 0 1 2 0 | 80000000 00000000 12340000 0 -- Setup Int interrupt 0 00000000 0 1 0 0 | C0000000 00000000 12340000 0 -- Check went through 0 00000000 0 1 0 0 | C0000000 00000000 12340000 0 -- And stays 0 60000000 1 1 0 0 | C0000000 00000000 12340000 0 -- Acknowledge all ITs 0 00000000 0 1 0 0 | 80000000 00000000 12340000 0 -- Check cleared exactly one 0 60000000 1 1 2 0 | 80000000 00000000 12340000 0 -- Check that Int overrides Ack 0 00000000 0 1 0 0 | C0000000 00000000 12340000 0 -- Must have interrupt 0 60000000 1 1 0 0 | C0000000 00000000 12340000 0 -- Remove it 0 00000000 0 1 0 0 | 80000000 00000000 12340000 0 -- Done 0 00000000 0 0 0 0 | 80000000 00000000 12340000 0 -- Remove all interrupts 0 00000000 0 0 0 0 | 80000000 00000000 12340000 0 -- (takes 2 cycles) 0 00000000 0 0 0 0 | 00000000 00000000 12340000 0 0 DFABCDEF 2 0 0 0 | 00000000 00000000 12340000 0 -- Setup mask 0 00000000 0 0 0 0 | 00000000 C0000000 12340000 0 -- Check only 3 MSB stored 0 00000000 0 1 0 0 | 00000000 C0000000 12340000 0 -- Raise an INT that's masked 0 00000000 0 1 1 0 | 00000000 C0000000 12340000 0 -- Add a visible IntIntr 0 00000000 0 1 0 0 | A0000000 C0000000 12340000 0 -- both visible simultaneously! 0 00000000 0 1 0 0 | A0000000 C0000000 12340000 1 -- 2nd IT rqrs service 0 00000000 0 1 0 0 | A0000000 C0000000 12340000 1 -- Nothing changed 0 00000000 0 1 0 1 | A0000000 C0000000 12340000 1 -- Service it 0 00000000 0 1 0 0 | A0000000 C0000000 12340000 0 -- No more srvc rqrd 0 00000000 0 1 0 0 | A0000000 C0000000 12340000 0 -- Should not reappear 0 20000000 2 1 0 0 | A0000000 C0000000 12340000 0 -- Unmask pending IT 0 00000000 0 1 0 0 | A0000000 20000000 12340000 0 -- Mask updated 0 00000000 0 1 0 0 | A0000000 20000000 12340000 1 -- Pending interrupt rqrs srvc 0 00000000 0 1 0 0 | A0000000 20000000 12340000 1 -- Pending interrupt rqrs srvc 0 00000000 0 1 0 1 | A0000000 20000000 12340000 1 -- Service it 0 00000000 0 1 0 0 | A0000000 20000000 12340000 0 -- No more service pending . κIOBITRegs.oracle Jean-Marc Frailong February 27, 1987 3:36:18 pm PST This file assumes 6 external interrupts and 2 internal ones, for a grand total of 8 interrupts (helps keeping nibble structure...). The file is designed to end by an error (on purpose) at cycle 80. Outputs: Reset (0), DIn (32), WRSelect (2: 0->none, 1->WRAck, 2->WRMask, 3->WRReason), INT (0), IntIntr (2), ITSrvDone (0) Inputs: StatusOut (32), MaskOut (32), ReasonOut (32), ITSrvRqrd (0) Reset DIn WRSelect INT IntIntr ITSrvDone | StatusOut MaskOut ReasonOut ITSrvRqrd -- Comment Test of the IOB Interrupt registers Reset sequence Initialize Reason, won't touch it any more Check INT works Check IntIntr work Check mask and interrupt servicing Κq˜šœ™Icode™3—J˜J™ƒJ™AJ™™J™qJ™—™J™;—J™Jš,ΠftΟfžžžžžžžžžž žž žžžž žž ΠcfΟcΠct ‘™qJ™head™#™Jšž1Ÿ ˜BJšž1Ÿ ˜BJšž1Ÿ ˜HJšž1Ÿ ˜L—™*Jšž1Ÿ ˜AJšž1Ÿ  ˜R—™Jšž1Ÿ  ˜>Jšž1˜1Jšž1˜1Jšž1Ÿ ˜I—™Jšž1Ÿ ˜HJšž1Ÿ ˜GJšž1Ÿ  ˜>Jšž1Ÿ ˜HJšž1Ÿ ˜NJšž1Ÿ ˜QJšž1Ÿ ˜HJšž1Ÿ  ˜>Jšž1Ÿ ˜9—™"Jšž1Ÿ ˜JJšž1Ÿ ˜EJšž1˜1Jšž1Ÿ  ˜?Jšž1Ÿ ˜LJ˜Jšž1Ÿ ˜OJšž1Ÿ ˜JJšž1Ÿ ˜QJšž1Ÿ ˜HJšž1Ÿ ˜DJšž1Ÿ  ˜?Jšž1Ÿ ˜FJšž1Ÿ ˜HJ˜Jšž1Ÿ ˜FJšž1Ÿ ˜AJšž1Ÿ ˜PJšž1Ÿ ˜PJšž1Ÿ  ˜?Jšž1Ÿ ˜L—J˜—J˜—…— tΟ