ColorDisplayModeOff CDCMosB Install IOBridge SC PadFrames _ CedarProcess.SetPriority[background] Statistics on CDRead IOBridge _ &design _ CDViewer.FindDesign["IOBridge"] _ &cx _ Sisyph.Create[&design, NIL] _ &ct _ Sisyph.ES["IOBridge.sch", &cx] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ &scBlock _ Sisyph.ES["IOBInnerSC.sch", &cx] _ PWCore.Layout[&scBlock] _ PWCore.Store[&scBlock, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ &ob _ PWCore.Layout[&ct] _ PW.Draw[&ob] _ PWCore.Store[&ct, FALSE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 Install PWCoreLichen _ PWCoreLichen.SetAutomorphismHack[TRUE] _ PWCoreLichen.Compare[&ct] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 Install ConnectivityChecker CheckConnectivity IOBridgeLayout.dale _ RoutingCheckImpl.Check[PW.OpenDesign["IOBridgeLayout.dale"]] ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 ΨIOBCountdown.cm Copyright Σ 1987 by Xerox Corporation. All rights reserved. Louis Monier October 12, 1987 11:14:55 am PDT Jean-Marc Frailong November 17, 1987 7:38:47 pm PST -- Goal -- This command file captures all the operations necessary to "finish" the IOBridge before fabrication. -- It is derived from LM's Countdown.cm -- Assumptions -- All libraries have been run through the DRC and Lichen (standard cells, pads, ram) and are frozen until the run goes out. -- The design is completed, has been simulated at transistor level, and some timing estimation made (Mint, Spice...) -- For power bus sizing, eyeball and be conservative. -- You have a df file pertaining to this chip; the df file must verify, so that you can switch between machines rapidly. -- You keep a daily log of your work on the chip (very useful when testing the wafers). -- Start everything, read in the source design and extract chip -- Saves quite a lot of time... -- _ TWOps.host _ "Tregonsee" -- Install all useful programs. Others may be added here, or later on the way (depending on RollBacks...) -- You always want to know how long it took -- Read the CD design & all its importees, then retrieve design -- Creates a context for Sisyph -- Extracts the top-level schematic -- Do a trace & sweep garbage collection and recover free pages -- Checks on the source cell type -- Apply Static Install Static _ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]] -- Errors can be found in the terminal -- Apply MintCheck (analysis of incorrect electric connections) on schematic Install Mint _ &circuit _ Mint.CreateCircuit[&ct] _ MintCmds.PrepareCircuit[&circuit, FALSE] _ Mint.CheckLibrary[&circuit] -- Errors can be found found in the terminal -- Make a note of this number of transistors, and write home about it -- You also get an estimation of the total capacitance which you can use to derive an upper bound on the average power consumption. _ Mint.KillCircuit[&circuit] _ &circuit _ NIL ForceReclaimFreePages 5; ForceReclaimFreePages 5 _ SafeStorage.ReclaimCollectibleObjects[TRUE, TRUE] ForceReclaimFreePages 5; ForceReclaimFreePages 5 -- Destroy circuit, do a trace & sweep garbage collection and recover free pages -- Simulate as completely as possible, at transistor level (assuming oracle) _ &oracle _ Sisyph.ES["IOBridge.test", &cx] -- Extracts the schematics containing the top-level cell with its oracle (assuming same design) -- use the "log" parameter on the oracle -- put an object property "Simulation: $Transistors" inside BICTransistorLevel.sim to be sure to simulate at transistor level; if you stay at gate level for example, your blind faith in Logic might cost you a lot. -- when simulating at transistor level, use a separate clock for the circuit and the oracle: up_2 and dn_2 on both, but firstEdge _ 2 on the circuit clock works well and preserves the oracle file. _ Ports.CoerceNewToOld[&oracle.public] _ Rosemary.SetFixedWire[CoreOps.FindWire[&oracle.public, "Vdd"], H] _ Rosemary.SetFixedWire[CoreOps.FindWire[&oracle.public, "Gnd"], L] _ &tester _ RosemaryUser.TestProcedureViewer[cellType: &oracle, testButtons: LIST["Logic Test"], name: "IOBridge transistor level test", cutSet: NIL] _ RosemaryUser.StartTest[&tester] -- Batch mode for oracle. open ///Temp/InterfaceChip.bugs The log of all bugs found during the simulation; if empty, no bugs -- Generate Layout -- Build the layout for the SC part (this needs to be done in a first step in order to GC all) -- and save it (who knows...) -- Do a trace & sweep garbage collection and recover free pages -- Creates the CD object and attaches it to the cellType -- Just a viewer; don't edit or save it -- Saves the decorated Core under IOBridge.core, the layout under IOBridgeLayout.dale, and a view of the public pins under IOBridgeShell.dale -- The decorated Core will be read back for future work -- The layout will be DRCed, plotted, and turned into a Mebes file -- The shell will be needed to check the pad position and make the probing and bonding maps -- Do a trace & sweep garbage collection and recover free pages -- Checks on the generated layout -- Compare layout and schematics _ CoreProperties.PutCellTypeProp[on: &ct, prop: $LichenTransistorTolerances, value: "0.8, 0.8"] That's length and width, commented out for the time being... -- Compares the cellType with the extracted layout -- Do a trace & sweep garbage collection and recover free pages -- Check the connectivity -- Signals all disconnected internals; returns a list of disconnected publics -- Checks for shorts in routing cells -- Do a trace & sweep garbage collection and recover free pages -- Check design rules -- No programming interface right now... -- Plots CDPlot Sleepy -k IOBridgeLayout -- Plot IOBridgeLayout.dale and eyeball it -- Production files -- Bonding map -- Use the shell to produce a bonding map; make sure that all bonding and wiring constraints are satisfied -- Generate the Mebes files (project IOBNOV87A) MEBESConvert16Nov87CMOSBDesign -- Will ask 3 questions: -- - n+ to p+ spacing: 12 um -- - file name: IOBridgeLayout -- - project name: IOBNOV87A -- SModel under /indigo/dragon7.0/IOBNOV87A.df and archive immediately -- To be written -- Visit your travel agent for good prices for Tahiti... Κπ˜™Icode™Jšœ%™%—J˜0Jšœ(œœ˜3˜0J™?——šœ™K™(——šœ™šœ™Jšœ*™*——™™Jšœj™j—šœ/™/šœ™™Jšœ™Jšœ™J™————šœF™FJ™—L™8J˜—…—t<