IOMgrCtl.oracle
Jean-Marc Frailong March 9, 1987 11:42:25 pm PST
Test of the IOBridge I/O manager controller (DynaBus slave).
DynaBus commands are 10 (IOReadRequest), 12 (IOWriteRequest), 14 (BIOWriteRequest)
Inputs:
Reset (0), DataAvail (0), RpBusy (0), IOBusDone (0), IOCheck (0), IORange (0), RegCmd (0), Kernel (0), CmdIn (5), RegAddr (3)
Outputs:
nIOBusStart (0), Pop (0), LdReply (0), Denied (0), BusErr (0), CmdOut (5), RegWR (8), PerRDSel (3)
Reset DataAvail RpBusy IOBusDone IOCheck IORange RegCmd Kernel CmdIn RegAddr | nIOBusStart Pop LdReply Denied BusErr CmdOut RegWR PerRDSel -- Comment
Test of the I/O manager controller
Reset sequence, check Reset disables all signals
1 0 X X X X X X XX X | X X X X X XX XX X -- Outputs unknown
1 0 X X X X X X XX X | X X X X X XX XX X -- Outputs unknown
0 0 X X X X X X XX X | 1 0 0 X X XX 00 X -- Outputs settled now
Register Read cycles
Read reg 0, Fifo remains full
0 1 X X X X X X XX X | 1 0 0 X X XX 00 X -- Initiate cycle - $Idle
0 1 0 X X X X X XX X | 1 1 0 X X XX 00 X -- $Pop
0 1 0 X X 1 1 1 10 0 | 1 0 0 0 0 11 00 7 -- $Decode
0 1 0 X X 1 1 1 10 0 | 1 0 1 0 0 11 00 7 -- $Rp
Read reg 1, Fifo remains full
0 1 1 X X 1 1 1 10 0 | 1 1 0 0 0 11 00 7 -- $Pop
0 1 0 X X 1 1 1 10 1 | 1 0 0 0 0 11 00 6 -- $Decode
0 1 0 X X 1 1 1 10 1 | 1 0 1 0 0 11 00 6 -- $Rp
Read reg 2, Fifo remains full
0 1 1 X X 1 1 1 10 1 | 1 1 0 0 0 11 00 6 -- $Pop
0 1 0 X X 1 1 1 10 2 | 1 0 0 0 0 11 00 5 -- $Decode
0 1 0 X X 1 1 1 10 2 | 1 0 1 0 0 11 00 5 -- $Rp
Read reg 3, Fifo remains full, reply busy for some time
0 1 1 X X 1 1 1 10 2 | 1 1 0 0 0 11 00 5 -- $Pop
0 1 1 X X 1 1 1 10 3 | 1 0 0 0 0 11 00 4 -- $Decode, but wait before sending reply
0 1 1 X X 1 1 1 10 3 | 1 0 0 0 0 11 00 4 -- $WaitRp
0 1 1 X X 1 1 1 10 3 | 1 0 0 0 0 11 00 4 -- $WaitRp
0 1 0 X X 1 1 1 10 3 | 1 0 0 0 0 11 00 4 -- $WaitRp
0 1 0 X X 1 1 1 10 3 | 1 0 1 0 0 11 00 4 -- $Rp
Read reg 4, Fifo remains full, check Kernel ignored
0 1 1 X X 1 1 1 10 3 | 1 1 0 0 0 11 00 4 -- $Pop
0 1 0 X X 1 1 0 10 4 | 1 0 0 0 0 11 00 3 -- $Decode, check Kernel bit ineffective
0 1 0 X X 1 1 0 10 4 | 1 0 1 0 0 11 00 3 -- $Rp
Read reg 5, Fifo becomes empty
0 1 1 X X 1 1 0 10 4 | 1 1 0 0 0 11 00 3 -- $Pop
0 1 0 X X 1 1 0 10 5 | 1 0 0 0 0 11 00 2 -- $Decode, check Kernel bit ineffective
0 0 0 X X 1 1 0 10 5 | 1 0 1 0 0 11 00 2 -- $Rp
0 0 1 X X 1 1 0 10 5 | 1 0 0 0 0 11 00 2 -- $Idle
0 0 1 X X 1 1 0 10 5 | 1 0 0 0 0 11 00 2 -- $Idle
Read reg 6, Fifo remains full
0 1 0 X X 1 1 0 10 5 | 1 0 0 0 0 11 00 2 -- $Idle, fifo has new data
0 1 0 X X 1 1 0 10 5 | 1 1 0 0 0 11 00 2 -- $Pop
0 1 0 X X 1 1 0 10 6 | 1 0 0 0 0 11 00 1 -- $Decode, check Kernel bit ineffective
0 1 0 X X 1 1 0 10 6 | 1 0 1 0 0 11 00 1 -- $Rp
Read reg 7, Fifo becomes empty
0 1 1 X X 1 1 0 10 6 | 1 1 0 0 0 11 00 1 -- $Pop
0 1 0 X X 1 1 1 10 7 | 1 0 0 0 0 11 00 0 -- $Decode
0 0 0 X X 1 1 1 10 7 | 1 0 1 0 0 11 00 0 -- $Rp
0 0 1 X X 1 1 1 10 7 | 1 0 0 0 0 11 00 0 -- $Idle
0 0 1 X X 1 1 1 10 7 | 1 0 0 0 0 11 00 0 -- $Idle
Register Write cycles
Write reg 0, Fifo remains full
0 1 X X X X X X XX X | 1 0 0 X X XX 00 X -- Initiate cycle - $Idle
0 1 0 X X X X X XX X | 1 1 0 X X XX 00 X -- $Pop
0 1 0 X X 1 1 1 12 0 | 1 0 0 0 0 13 00 7 -- $Decode
0 1 0 X X 1 1 1 12 0 | 1 0 1 0 0 13 20 7 -- $Rp
BIOWrite reg 1, Fifo remains full
0 1 1 X X 1 1 1 12 0 | 1 1 0 0 0 13 00 7 -- $Pop
0 1 0 X X 1 1 1 14 1 | 1 0 0 0 0 15 00 6 -- $Decode a BIOWrite
0 1 0 X X 1 1 1 14 1 | 1 0 0 0 0 15 10 6 -- $Rp
Write reg 2, Fifo remains full
0 1 1 X X 1 1 1 14 1 | 1 1 0 0 0 15 00 6 -- $Pop
0 1 0 X X 1 1 1 12 2 | 1 0 0 0 0 13 00 5 -- $Decode
0 1 0 X X 1 1 1 12 2 | 1 0 1 0 0 13 08 5 -- $Rp
Write reg 3, Fifo remains full, wait to send reply
0 1 1 X X 1 1 1 12 2 | 1 1 0 0 0 13 00 5 -- $Pop
0 1 1 X X 1 1 1 12 3 | 1 0 0 0 0 13 00 4 -- $Decode, but wait before sending reply
0 1 1 X X 1 1 1 12 3 | 1 0 0 0 0 13 00 4 -- $WaitRp
0 1 1 X X 1 1 1 12 3 | 1 0 0 0 0 13 00 4 -- $WaitRp
0 1 0 X X 1 1 1 12 3 | 1 0 0 0 0 13 00 4 -- $WaitRp
0 1 0 X X 1 1 1 12 3 | 1 0 1 0 0 13 04 4 -- $Rp
Write reg 4, Fifo remains full, Kernel bit not asserted (command denied)
0 1 1 X X 1 1 1 12 3 | 1 1 0 0 0 13 00 4 -- $Pop
0 1 0 X X 1 1 0 12 4 | 1 0 0 1 0 13 00 0 -- $Decode, check Kernel bit effective
0 1 0 X X 1 1 0 12 4 | 1 0 1 1 0 13 00 0 -- $Rp
Write reg 5, Fifo becomes empty
0 1 1 X X 1 1 0 12 4 | 1 1 0 1 0 13 00 0 -- $Pop
0 1 0 X X 1 1 1 12 5 | 1 0 0 0 0 13 00 2 -- $Decode
0 0 0 X X 1 1 1 12 5 | 1 0 1 0 0 13 01 2 -- $Rp
0 0 1 X X 1 1 1 12 5 | 1 0 0 0 0 13 00 2 -- $Idle
0 0 0 X X 1 1 1 12 5 | 1 0 0 0 0 13 00 2 -- $Idle
Write reg 6, Fifo remains full
0 1 0 X X 1 1 1 12 5 | 1 0 0 0 0 13 00 2 -- $Idle, new data available
0 1 0 X X 1 1 1 12 5 | 1 1 0 0 0 13 00 2 -- $Pop
0 1 0 X X 1 1 1 12 6 | 1 0 0 0 0 13 00 1 -- $Decode
0 1 0 X X 1 1 1 12 6 | 1 0 1 0 0 13 00 1 -- $Rp
Write reg 7, Fifo becomes empty
0 1 1 X X 1 1 1 12 6 | 1 1 0 0 0 13 00 1 -- $Pop
0 1 0 X X 1 1 1 12 7 | 1 0 0 0 0 13 00 0 -- $Decode
0 0 0 X X 1 1 1 12 7 | 1 0 1 0 0 13 00 0 -- $Rp
0 0 0 X X 1 1 1 12 7 | 1 0 0 0 0 13 00 0 -- $Idle
0 0 0 X X 1 1 1 12 7 | 1 0 0 0 0 13 00 0 -- $Idle
IOBus Read cycles
Read IOBus, wait for IOBus to complete
0 1 X X X X X X XX X | 1 0 0 X X XX 00 X -- Initiate cycle - $Idle
0 1 0 X X X X X XX X | 1 1 0 X X XX 00 X -- $Pop
0 1 0 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $Decode
0 1 0 0 0 1 0 1 10 X | 0 0 0 0 0 11 00 1 -- $IOBusStart
0 1 0 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $IOBusWait
0 1 0 1 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $IOBusWait
0 1 0 0 0 1 0 1 10 X | 1 0 1 0 0 11 00 1 -- $Rp
Read IOBus, get an IOBus error
0 1 1 0 0 1 0 1 10 X | 1 1 0 0 0 11 00 1 -- $Pop
0 1 1 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $Decode
0 1 0 0 0 1 0 1 10 X | 0 0 0 0 0 11 00 1 -- $IOBusStart
0 1 0 1 1 1 0 1 10 X | 1 0 0 0 1 11 00 0 -- $IOBusWait, bus error
0 1 0 0 1 1 0 1 10 X | 1 0 1 0 1 11 00 0 -- $Rp
Read IOBus, wait to send reply
0 1 1 0 1 1 0 1 10 X | 1 1 0 0 1 11 00 0 -- $Pop
0 1 1 0 1 1 0 1 10 X | 1 0 0 0 1 11 00 0 -- $Decode
0 0 1 0 1 1 0 1 10 X | 0 0 0 0 1 11 00 0 -- $IOBusStart
0 0 1 1 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $IOBusWait
0 0 1 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $WaitRp
0 0 1 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $WaitRp
0 0 0 0 0 1 0 1 10 X | 1 0 0 0 0 11 00 1 -- $WaitRp
0 0 0 0 0 1 0 1 10 X | 1 0 1 0 0 11 00 1 -- $Rp
0 0 1 X X 1 1 1 10 X | 1 0 0 0 0 11 00 X -- $Idle
0 0 1 X X 1 1 1 10 X | 1 0 0 0 0 11 00 X -- $Idle
IOBus Write cycles
Write IOBus, wait for IOBus to complete
0 1 X X X X X X XX X | 1 0 0 X X XX 00 X -- Initiate cycle - $Idle
0 1 0 X X X X X XX X | 1 1 0 X X XX 00 X -- $Pop
0 1 0 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $Decode
0 1 0 0 0 1 0 1 12 X | 0 0 0 0 0 13 00 1 -- $IOBusStart
0 1 0 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $IOBusWait
0 1 0 1 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $IOBusWait
0 1 0 0 0 1 0 1 12 X | 1 0 1 0 0 13 00 1 -- $Rp
Write IOBus, without Kernel bit
0 1 1 0 0 1 0 1 12 X | 1 1 0 0 0 13 00 1 -- $Pop
0 1 0 0 0 1 0 0 12 X | 1 0 0 1 0 13 00 0 -- $Decode
0 1 0 0 0 1 0 0 12 X | 1 0 1 1 0 13 00 0 -- $Rp
Write IOBus, get an IOBus error
0 1 1 0 0 1 0 0 12 X | 1 1 0 1 0 13 00 0 -- $Pop
0 1 0 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $Decode
0 1 0 0 0 1 0 1 12 X | 0 0 0 0 0 13 00 1 -- $IOBusStart
0 1 0 1 1 1 0 1 12 X | 1 0 0 0 1 13 00 0 -- $IOBusWait, bus error
0 1 0 0 1 1 0 1 12 X | 1 0 1 0 1 13 00 0 -- $Rp
Write IOBus, without Kernel bit while bus error is pending
0 1 1 0 1 1 0 1 12 X | 1 1 0 0 1 13 00 0 -- $Pop
0 1 0 0 1 1 0 0 12 X | 1 0 0 1 0 13 00 0 -- $Decode
0 1 0 0 1 1 0 0 12 X | 1 0 1 1 0 13 00 0 -- $Rp
Write IOBus, wait to send reply
0 1 1 0 1 1 0 1 12 X | 1 1 0 0 1 13 00 0 -- $Pop
0 1 1 0 1 1 0 1 12 X | 1 0 0 0 1 13 00 0 -- $Decode
0 0 1 0 1 1 0 1 12 X | 0 0 0 0 1 13 00 0 -- $IOBusStart
0 0 1 1 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $IOBusWait
0 0 1 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $WaitRp
0 0 1 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $WaitRp
0 0 0 0 0 1 0 1 12 X | 1 0 0 0 0 13 00 1 -- $WaitRp
0 0 0 0 0 1 0 1 12 X | 1 0 1 0 0 13 00 1 -- $Rp
0 0 1 X X 1 1 1 12 X | 1 0 0 0 0 13 00 X -- $Idle
0 0 1 X X 1 1 1 12 X | 1 0 0 0 0 13 00 X -- $Idle
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