[_CD4_]<dragon7.0>IOBridge>IOBusMaster.oracle!1

IOBusMaster.oracle

Jean-Marc Frailong March 4, 1987 0:11:30 am PST

Test of the IOBus master (complete)

Test correct function of the automaton, random logic and data path (byte swapping)

Inputs:

Reset (0), BAck (0), nReady (0), nStart (0), IORange (0), RdCmd (0), Addr (32), DIn (32)

Outputs:

BReq (0), IOBAddrOut (24), nBHEOut (0), IOBDOut (16), INTA (0), IOR (0), IOW (0), RD (0), WR (0), nDT/R (0), AEN (0), DOut (32)

Reset BAck nReady nStart IORange RdCmd Addr DIn IOBDIn | BReq IOBAddrOut nBHEOut IOBDout INTA IOR IOW RD WR nDT/R nDEN AEN DOut -- Comment

Test of the IOBus master

Reset sequence

1 1 0 1 0 0 20000000 00000000 XXXX | X XXXXXX X XXXX X X X X X X X X XXXXXXXX -- Reset

0 1 0 1 0 0 20000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Reset complete

Memory Read tests, 0 wait states & no bus grant delay

For all memory read tests, memory is supposed to contain 12, 34, 56, 78 at address 0, 1, 2, 3. This means that the byte order should be (12345678), the INT16 order (34127856) (or 78563412) and the INT32 order (78563412).

Memory Read byte cycle with even address

0 1 0 1 0 1 20000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 20000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 20000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 20000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 20000002 00000000 XXXX | 1 000002 1 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 20000002 00000000 XXXX | 1 000002 1 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 20000002 00000000 XX56 | 1 000002 1 XXXX 0 0 0 1 0 1 0 1 000000XX -- C1, T3

0 1 0 1 0 1 20000002 00000000 XX56 | 1 000002 1 XXXX 0 0 0 1 0 1 0 1 00000056 -- C1, T4

0 1 0 1 0 1 20000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00000056 -- Idle

Memory Read byte cycle with odd address

0 1 0 1 0 1 20000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 20000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 20000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 20000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 20000003 00000000 XXXX | 1 000003 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 20000003 00000000 XXXX | 1 000003 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 20000003 00000000 78XX | 1 000003 0 XXXX 0 0 0 1 0 1 0 1 000000XX -- C1, T3

0 1 0 1 0 1 20000003 00000000 78XX | 1 000003 0 XXXX 0 0 0 1 0 1 0 1 00000078 -- C1, T4

0 1 0 1 0 1 20000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00000078 -- Idle

Memory Read word cycle with even address

0 1 0 1 0 1 30000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 30000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 30000000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 30000000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 30000000 00000000 XXXX | 1 000000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 30000000 00000000 XXXX | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 30000000 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 30000000 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00003412 -- C1, T4

0 1 0 1 0 1 30000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00003412 -- Idle

Memory Read word cycle with odd address

0 1 0 1 0 1 30000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 30000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 30000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 30000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 30000003 00000000 XXXX | 1 000002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 30000003 00000000 XXXX | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 30000003 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 30000003 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00005678 -- C1, T4

0 1 0 1 0 1 30000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00005678 -- Idle

Memory Read long cycle with 0 mod 4 address

0 1 0 1 0 1 40000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 40000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 40000000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 40000000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 40000000 00000000 XXXX | 1 000000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 40000000 00000000 XXXX | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 40000000 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 40000000 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00003412 -- C1, T4

0 1 0 1 0 1 40000000 00000000 XXXX | 1 000002 0 XXXX 0 0 0 0 0 1 1 1 00003412 -- C2, T1

0 1 0 1 0 1 40000000 00000000 XXXX | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00003412 -- C2, T2

0 1 0 1 0 1 40000000 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 XXXX3412 -- C2, T3

0 1 0 1 0 1 40000000 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 78563412 -- C2, T4

0 1 0 1 0 1 40000000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 78563412 -- Idle

Memory Read long cycle with 1 mod 4 address

0 1 0 1 0 1 40000001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 40000001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 40000001 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 40000001 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 40000001 00000000 XXXX | 1 000000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 40000001 00000000 XXXX | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 40000001 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 40000001 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00001234 -- C1, T4

0 1 0 1 0 1 40000001 00000000 XXXX | 1 000002 0 XXXX 0 0 0 0 0 1 1 1 00001234 -- C2, T1

0 1 0 1 0 1 40000001 00000000 XXXX | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00001234 -- C2, T2

0 1 0 1 0 1 40000001 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 XXXX1234 -- C2, T3

0 1 0 1 0 1 40000001 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 56781234 -- C2, T4

0 1 0 1 0 1 40000001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 56781234 -- Idle

Memory Read long cycle with 2 mod 4 address

0 1 0 1 0 1 40000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 40000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 40000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 40000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 40000002 00000000 XXXX | 1 000002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 40000002 00000000 XXXX | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 40000002 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 40000002 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00007856 -- C1, T4

0 1 0 1 0 1 40000002 00000000 XXXX | 1 000000 0 XXXX 0 0 0 0 0 1 1 1 00007856 -- C2, T1

0 1 0 1 0 1 40000002 00000000 XXXX | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00007856 -- C2, T2

0 1 0 1 0 1 40000002 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 XXXX7856 -- C2, T3

0 1 0 1 0 1 40000002 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 34127856 -- C2, T4

0 1 0 1 0 1 40000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 34127856 -- Idle

Memory Read long cycle with 3 mod 4 address

0 1 0 1 0 1 40000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 1 40000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 1 40000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 1 40000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 1 40000003 00000000 XXXX | 1 000002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 0 1 40000003 00000000 XXXX | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00000000 -- C1, T2

0 1 0 1 0 1 40000003 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 0 1 40000003 00000000 7856 | 1 000002 0 XXXX 0 0 0 1 0 1 0 1 00005678 -- C1, T4

0 1 0 1 0 1 40000003 00000000 XXXX | 1 000000 0 XXXX 0 0 0 0 0 1 1 1 00005678 -- C2, T1

0 1 0 1 0 1 40000003 00000000 XXXX | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 00005678 -- C2, T2

0 1 0 1 0 1 40000003 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 XXXX5678 -- C2, T3

0 1 0 1 0 1 40000003 00000000 3412 | 1 000000 0 XXXX 0 0 0 1 0 1 0 1 12345678 -- C2, T4

0 1 0 1 0 0 40000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 12345678 -- Idle

Memory Write tests, 0 wait states & no bus grant delay

All the write tests use the same value (12345678) for the data to be written

Memory Write byte cycle with even address

0 1 0 1 0 0 20000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 20000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 20000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 20000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 20000002 12345678 XXXX | 1 000002 1 XX78 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 20000002 12345678 XXXX | 1 000002 1 XX78 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 20000002 12345678 XXXX | 1 000002 1 XX78 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 20000002 12345678 XXXX | 1 000002 1 XX78 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 20000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write byte cycle with odd address

0 1 0 1 0 0 20000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 20000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 20000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 20000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 20000003 12345678 XXXX | 1 000003 0 78XX 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 20000003 12345678 XXXX | 1 000003 0 78XX 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 20000003 12345678 XXXX | 1 000003 0 78XX 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 20000003 12345678 XXXX | 1 000003 0 78XX 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 20000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write word cycle with even address

0 1 0 1 0 0 30000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 30000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 30000000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 30000000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 30000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 30000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 30000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 30000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 30000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write word cycle with odd address

0 1 0 1 0 0 30000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 30000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 30000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 30000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 30000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 30000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 30000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 30000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 30000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write long cycle with 0 mod 4 address

0 1 0 1 0 0 40000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 40000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 40000000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 40000000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000000 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000002 0 1234 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000002 0 1234 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000002 0 1234 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 0 0 40000000 12345678 XXXX | 1 000002 0 1234 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 0 0 40000000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write long cycle with 1 mod 4 address

0 1 0 1 0 0 40000001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 40000001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 40000001 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 40000001 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000000 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000000 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000000 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000000 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000002 0 3412 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000002 0 3412 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000002 0 3412 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 0 0 40000001 12345678 XXXX | 1 000002 0 3412 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 0 0 40000001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write long cycle with 2 mod 4 address

0 1 0 1 0 0 40000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 40000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 40000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 40000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000002 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000002 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000002 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000002 0 5678 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000000 0 1234 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000000 0 1234 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000000 0 1234 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 0 0 40000002 12345678 XXXX | 1 000000 0 1234 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 0 0 40000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Memory Write long cycle with 3 mod 4 address

0 1 0 1 0 0 40000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 0 0 40000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 0 0 40000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 0 0 40000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000002 0 7856 0 0 0 0 1 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000000 0 3412 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000000 0 3412 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000000 0 3412 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 0 0 40000003 12345678 XXXX | 1 000000 0 3412 0 0 0 0 1 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 0 0 40000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Read tests, 0 wait states & no bus grant delay

For all I/O read tests, memory is supposed to contain 12, 34, 56, 78 at address 0, 1, 2, 3. This means that the byte order should be (12345678), the INT16 order (34127856) (or 78563412) and the INT32 order (78563412).

I/O Read byte cycle with even address

0 1 0 1 1 1 00000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00000002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00000002 00000000 XXXX | 1 XX0002 1 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00000002 00000000 XXXX | 1 XX0002 1 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00000002 00000000 XX56 | 1 XX0002 1 XXXX 0 1 0 0 0 1 0 1 000000XX -- C1, T3

0 1 0 1 1 1 00000002 00000000 XX56 | 1 XX0002 1 XXXX 0 1 0 0 0 1 0 1 00000056 -- C1, T4

0 1 0 1 1 1 00000002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00000056 -- Idle

I/O Read byte cycle with odd address

0 1 0 1 1 1 00000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00000003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00000003 00000000 XXXX | 1 XX0003 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00000003 00000000 XXXX | 1 XX0003 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00000003 00000000 78XX | 1 XX0003 0 XXXX 0 1 0 0 0 1 0 1 000000XX -- C1, T3

0 1 0 1 1 1 00000003 00000000 78XX | 1 XX0003 0 XXXX 0 1 0 0 0 1 0 1 00000078 -- C1, T4

0 1 0 1 1 1 00000003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00000078 -- Idle

I/O Read word cycle with even address

0 1 0 1 1 1 00010000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00010000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00010000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00010000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00010000 00000000 XXXX | 1 XX0000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00010000 00000000 XXXX | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00010000 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00010000 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00003412 -- C1, T4

0 1 0 1 1 1 00010000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00003412 -- Idle

I/O Read word cycle with odd address

0 1 0 1 1 1 00010003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00010003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00010003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00010003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00010003 00000000 XXXX | 1 XX0002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00010003 00000000 XXXX | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00010003 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00010003 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00005678 -- C1, T4

0 1 0 1 1 1 00010003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00005678 -- Idle

I/O Read long cycle with 0 mod 4 address

0 1 0 1 1 1 00020000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00020000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XX0000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00020000 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00020000 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00003412 -- C1, T4

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XX0002 0 XXXX 0 0 0 0 0 1 1 1 00003412 -- C2, T1

0 1 0 1 1 1 00020000 00000000 XXXX | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00003412 -- C2, T2

0 1 0 1 1 1 00020000 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 XXXX3412 -- C2, T3

0 1 0 1 1 1 00020000 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 78563412 -- C2, T4

0 1 0 1 1 1 00020000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 78563412 -- Idle

I/O Read long cycle with 1 mod 4 address

0 1 0 1 1 1 00020001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00020001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XX0000 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00020001 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00020001 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00001234 -- C1, T4

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XX0002 0 XXXX 0 0 0 0 0 1 1 1 00001234 -- C2, T1

0 1 0 1 1 1 00020001 00000000 XXXX | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00001234 -- C2, T2

0 1 0 1 1 1 00020001 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 XXXX1234 -- C2, T3

0 1 0 1 1 1 00020001 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 56781234 -- C2, T4

0 1 0 1 1 1 00020001 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 56781234 -- Idle

I/O Read long cycle with 2 mod 4 address

0 1 0 1 1 1 00020002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00020002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XX0002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00020002 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00020002 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00007856 -- C1, T4

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XX0000 0 XXXX 0 0 0 0 0 1 1 1 00007856 -- C2, T1

0 1 0 1 1 1 00020002 00000000 XXXX | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00007856 -- C2, T2

0 1 0 1 1 1 00020002 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 XXXX7856 -- C2, T3

0 1 0 1 1 1 00020002 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 34127856 -- C2, T4

0 1 0 1 1 1 00020002 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 34127856 -- Idle

I/O Read long cycle with 3 mod 4 address

0 1 0 1 1 1 00020003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00020003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XX0002 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00020003 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 0000XXXX -- C1, T3

0 1 0 1 1 1 00020003 00000000 7856 | 1 XX0002 0 XXXX 0 1 0 0 0 1 0 1 00005678 -- C1, T4

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XX0000 0 XXXX 0 0 0 0 0 1 1 1 00005678 -- C2, T1

0 1 0 1 1 1 00020003 00000000 XXXX | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 00005678 -- C2, T2

0 1 0 1 1 1 00020003 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 XXXX5678 -- C2, T3

0 1 0 1 1 1 00020003 00000000 3412 | 1 XX0000 0 XXXX 0 1 0 0 0 1 0 1 12345678 -- C2, T4

0 1 0 1 1 0 00020003 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 12345678 -- Idle

I/O Write tests, 0 wait states & no bus grant delay

All the I/O write tests use the same value (12345678) for the data to be written

I/O Write byte cycle with even address

0 1 0 1 1 0 00000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XX0002 1 XX78 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XX0002 1 XX78 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XX0002 1 XX78 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00000002 12345678 XXXX | 1 XX0002 1 XX78 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00000002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write byte cycle with odd address

0 1 0 1 1 0 00000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XX0003 0 78XX 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XX0003 0 78XX 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XX0003 0 78XX 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00000003 12345678 XXXX | 1 XX0003 0 78XX 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00000003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write word cycle with even address

0 1 0 1 1 0 00010000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00010000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XX0000 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XX0000 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XX0000 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00010000 12345678 XXXX | 1 XX0000 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00010000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write word cycle with odd address

0 1 0 1 1 0 00010003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00010003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XX0002 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XX0002 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XX0002 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00010003 12345678 XXXX | 1 XX0002 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00010003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write long cycle with 0 mod 4 address

0 1 0 1 1 0 00020000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00020000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0000 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0000 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0000 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0000 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0002 0 1234 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0002 0 1234 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0002 0 1234 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 1 0 00020000 12345678 XXXX | 1 XX0002 0 1234 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 1 0 00020000 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write long cycle with 1 mod 4 address

0 1 0 1 1 0 00020001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00020001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0000 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0000 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0000 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0000 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0002 0 3412 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0002 0 3412 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0002 0 3412 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 1 0 00020001 12345678 XXXX | 1 XX0002 0 3412 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 1 0 00020001 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write long cycle with 2 mod 4 address

0 1 0 1 1 0 00020002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00020002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0002 0 5678 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0002 0 5678 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0002 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0002 0 5678 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0000 0 1234 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0000 0 1234 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0000 0 1234 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 1 0 00020002 12345678 XXXX | 1 XX0000 0 1234 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 1 0 00020002 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

I/O Write long cycle with 3 mod 4 address

0 1 0 1 1 0 00020003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 0 00020003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0002 0 7856 0 0 0 0 0 0 1 1 XXXXXXXX -- C1, T1

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0002 0 7856 0 0 0 0 0 0 0 1 XXXXXXXX -- C1, T2

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0002 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T3

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0002 0 7856 0 0 1 0 0 0 0 1 XXXXXXXX -- C1, T4

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0000 0 3412 0 0 0 0 0 0 1 1 XXXXXXXX -- C2, T1

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0000 0 3412 0 0 0 0 0 0 0 1 XXXXXXXX -- C2, T2

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0000 0 3412 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T3

0 1 0 1 1 0 00020003 12345678 XXXX | 1 XX0000 0 3412 0 0 1 0 0 0 0 1 XXXXXXXX -- C2, T4

0 1 0 1 1 0 00020003 12345678 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Idle

Interrupt acknowledge test, 0 wait states & no bus grant delay

The vector returned should be 78.

Interrupt acknowledge cycle

0 1 0 1 1 1 00030000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Establish

0 1 0 0 1 1 00030000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Start cycle

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- Req

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX X XXXX 0 0 0 0 0 X X 0 XXXXXXXX -- W

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 0 0 0 0 0 1 1 1 00000000 -- C1, T1

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 00000000 -- C1, T2

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 000000XX -- C1, T3

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 000000XX -- C1, T4

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 0 0 0 0 0 1 1 1 000000XX -- C2, T1

0 1 0 1 1 1 00030000 00000000 XXXX | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 000000XX -- C2, T2

0 1 0 1 1 1 00030000 00000000 XX78 | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 000000XX -- C2, T3

0 1 0 1 1 1 00030000 00000000 XX78 | 1 XXXXXX 0 XXXX 1 0 0 0 0 1 0 1 00000078 -- C2, T4

0 1 0 1 1 1 00030000 00000000 XXXX | 0 XXXXXX X XXXX 0 0 0 0 0 X X 0 00000078 -- Idle