IOBusMCycle.oracle
Jean-Marc Frailong March 5, 1987 2:46:56 pm PST
Test of the IOBus master cycle generator.
Warning: the clock for the circuit is half the oracle clock. First line of oracle is for a rising edge of the circuit clock.
Inputs:
Reset (0), nStart (0), X2Cy (0), BAck (0), nReady (0)
Outputs:
BReq (0), AEN (0), IsCy2 (0), gateWRDEN (0), gateRD (0), gateWR (0), PreCycle (0), EOTr (0)
Reset nStart X2Cy BAck nReady | BReq AEN IsCy2 gateWRDEN gateRD gateWR PreCycle EOTr -- Comment
Test of the IOBus master cycle generator
Reset sequence, check Reset disables all signals
1 1 0 0 1 | X X X X X X X X -- CK^, Unknown state
1 1 0 0 1 | X X X X X X X X -- CK!, Unknown state
1 1 0 0 1 | X X X X X X X X -- CK^, Unknown state
1 1 0 0 1 | 0 0 0 X X X X X -- CK!, Unknown state for nCK FFs
1 1 0 0 1 | 0 0 0 0 X X X X -- CK^, should reset gateWRDEN
1 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, should reset all others
1 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
1 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK!, wiggle BAck and check nothing changes
1 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
1 1 0 0 0 | 0 0 0 0 0 0 0 0 -- CK!, wiggle nReady and check nothing changes
1 1 0 0 0 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, remove Reset
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, check for one more cycle to be sure
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
Wiggle various inputs while Idle
Try BAck
0 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
Try nReady
0 1 0 0 0 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 0 0 0 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
Try X2Cy
0 1 1 0 1 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 1 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, nothing changes
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing changes
Double bus cycle, 0WS, then 1WS
Take bus ownership
0 0 1 0 1 | 0 0 0 0 0 0 0 0 -- CK!, Start bus request automaton
0 0 1 0 1 | 1 0 0 0 0 0 0 0 -- CK^, Cycle started: (Req, T1)
0 1 1 0 1 | 1 0 0 0 0 0 0 0 -- CK!, check state remains when nStart removed
0 1 1 0 1 | 1 0 0 0 0 0 0 0 -- CK^, state: (Req, T1)
0 1 1 0 1 | 1 0 0 0 0 0 0 0 -- CK!, wait for BAck
0 1 1 0 1 | 1 0 0 0 0 0 0 0 -- CK^, state: (Req, T1)
0 1 1 1 1 | 1 0 0 0 0 0 0 0 -- CK!, provide BAck
0 1 1 1 1 | 1 0 0 0 0 0 1 0 -- CK^, state: (W, T1)
0 1 1 1 1 | 1 0 0 0 0 0 1 0 -- CK!, provide BAck
0 1 1 1 1 | 1 1 0 0 0 0 0 0 -- CK^, state: (C1, T1)
First cycle, 0 wait states
0 1 1 1 1 | 1 1 0 0 0 0 0 0 -- CK!, cycle FSA will start
0 1 1 1 1 | 1 1 0 1 1 0 0 0 -- CK^, Cycle started: (C1, T2)
0 1 1 1 1 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T2+)
0 1 1 1 0 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T3) - Assert Ready before mid-T3
0 1 1 1 0 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T3+)
0 1 1 1 0 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T4)
0 1 1 1 0 | 1 1 0 1 0 0 0 0 -- CK!, end all except gateWRDEN at (C1, T4+)
0 1 1 1 0 | 1 1 1 0 0 0 0 0 -- CK^, Cycle started: (C2, T1) - remove DEN, set X2Cy
Second cycle, 1 wait states
0 1 1 1 0 | 1 1 1 0 0 0 0 0 -- CK!, cycle FSA will start
0 1 1 1 1 | 1 1 1 1 1 0 0 0 -- CK^, Cycle started: (C2, T2)
0 1 1 1 1 | 1 1 1 1 1 1 0 0 -- CK!, now at (C2, T2+)
0 1 1 1 1 | 1 1 1 1 1 1 0 0 -- CK^, Cycle started: (C2, T3)
0 1 1 1 1 | 1 1 1 1 1 1 0 0 -- CK!, now at (C2, T3+)
0 1 1 1 0 | 1 1 1 1 1 1 0 0 -- CK^, Cycle started: (C2, T4), prepare nReady
0 1 1 1 0 | 1 1 1 1 1 1 0 0 -- CK!, now at (C2, T4+), not ready
0 1 1 1 0 | 1 1 1 1 1 1 0 0 -- CK^, Cycle started: (C2, T4)
0 1 1 1 0 | 1 1 1 1 0 0 0 1 -- CK!, end all except gateWRDEN at (C2, T4+)
0 1 1 1 0 | 0 0 0 0 0 0 0 0 -- CK^, Cycle started: (Idle, T1) - all inactive
Termination check
0 1 1 1 0 | 0 0 0 0 0 0 0 0 -- CK!, keep BAck to see...
0 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing should happen
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, be really idle
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing should happen
Single bus cycle, 2WS
Take bus ownership
0 0 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, Start bus request automaton
0 0 0 0 1 | 1 0 0 0 0 0 0 0 -- CK^, Cycle started: (Req, T1)
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK!, check state remains when nStart removed
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK^, state: (Req, T1)
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK!, wait for BAck
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK^, state: (Req, T1)
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK!, wait for BAck
0 1 0 0 1 | 1 0 0 0 0 0 0 0 -- CK^, state: (Req, T1)
0 1 0 1 1 | 1 0 0 0 0 0 0 0 -- CK!, provide BAck
0 1 0 1 1 | 1 0 0 0 0 0 1 0 -- CK^, state: (W, T1)
0 1 0 1 1 | 1 0 0 0 0 0 1 0 -- CK!, provide BAck
0 1 0 1 1 | 1 1 0 0 0 0 0 0 -- CK^, state: (C1, T1)
First (and only) cycle, 2 wait states
0 1 0 1 1 | 1 1 0 0 0 0 0 0 -- CK!, cycle FSA will start
0 1 0 1 1 | 1 1 0 1 1 0 0 0 -- CK^, Cycle started: (C1, T2)
0 1 0 1 1 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T2+)
0 1 0 1 1 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T3) - Assert Ready before mid-T3
0 1 0 1 1 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T3+)
0 1 0 1 1 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T4)
0 1 0 1 1 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T4+) - not ready yet
0 1 0 1 0 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T4) - Assert Ready before mid-T4
0 1 0 1 0 | 1 1 0 1 1 1 0 0 -- CK!, now at (C1, T4+) - not ready yet
0 1 0 1 0 | 1 1 0 1 1 1 0 0 -- CK^, Cycle started: (C1, T4)
0 1 0 1 0 | 1 1 0 1 0 0 0 1 -- CK!, end all except gateWRDEN at (C1, T4+)
0 1 0 1 0 | 0 0 0 0 0 0 0 0 -- CK^, Cycle started: (Idle, T1) - all inactive
Termination check
0 1 1 1 0 | 0 0 0 0 0 0 0 0 -- CK!, keep BAck to see...
0 1 0 1 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing should happen
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, be really idle
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK^, nothing should happen
Balance parity of number of cycles
0 1 0 0 1 | 0 0 0 0 0 0 0 0 -- CK!, Idle
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