[_CD4_]<dragon7.0>IOBridge>IOBusDoc.tioga!4

IOBUS DESCRIPTION

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

IOBus Description

The PC/AT interface for the June87 machine

Jean-Marc Frailong

Dragon-87-xx Written February 12, 1987 Revised May 1, 1987

Abstract: This document describes the IOBridge interface to the PC/AT I/O channel. After a summary of the structure of the PC/AT I/O channel, the complete specification of the IOBus is given, together with optional extensions to the PC/AT I/O channel to accomodate 32-bit addressing. Finally, a complete application schematic for interfacing the IOBridge to the PC/AT is given, and indications on the methods to be applied for multiple IOBridges are given.

Keywords: June87, IOBridge, IOBus, PC/AT

FileName: IOBusDoc.tioga, .interpress

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

Dragon Project - For Internal Xerox Use Only

Contents

1. A summary of the PC/AT I/O Channel

1.1. Glossary

1.2. PC/AT I/O Channel signals

1.3. PC/AT I/O Channel timing

1.4. Slave interface

1.5. Slave DMA interface

1.6. Master interface

1.7. Current mysteries of the PC/AT I/O channel

2. IOBus definition

2.1. General comments

2.2. Pin definition for extended addressing and decoded master control

2.3. Timings and clarifications

3. IOBridge application notes

3.1. Minimum application

3.2. PAL programming for minimum application

3.3. Interrupt management and DBus control

3.4. Hints for multi-IOBridge support

ChangeLog

1. A summary of the PC/AT I/O Channel

The PC/AT I/O channel is the bus that allows to plug additional peripherals and memory boards on the PC/AT system board. It is an extension of the PC I/O channel and carries along a lot of the latter's (mis)features.

1.1. Glossary

The PC/AT system uses the following expressions with a precise meaning:

System board The main board of the PC/AT. Contains the system CPU (80286) and is the only source of a number of system-wide signals.

Slave board A board that only answers to requests originated by other boards, but never issues requests of its own.

Slave DMA board A board that issues DMA requests but requires the system board to handle the address generation for its transfers.

Master DMA board A board that issues DMA requests and gains complete control of the I/O channel to issue its requests to slave boards. Shortened to Master board.

1.2. PC/AT I/O Channel signals

The following notations are used:

I Input to a board other than the system board

O Output from a board other than the system board

I/O Bidirectional signal (normally a tri-state port)

OC (R) Open collector (in fact a signal that a slave board may either pull down or float) with a pull-up of R ohms.

TSM Tri-state driven by the current bus master

M Issued by the system board

The PC/AT I/O channel carries the following signals:

Signal Direction Size Comments

SA0-SA19 I/O, TSM 20 20 low-order address bits, stable during a cycle (latched on the system board by BALE when CPU is bus master).

LA17-LA23 I/O, TSM 7 7 high-order address bits, valid at beginning of cycle only. Should be latched by slave devices using BALE. Warning: in the current versions of MS-DOS, the 80286 runs in real address mode. This means that LA20-LA23 are always low when running MS-DOS, resulting in only 1 Mbyte of address space. It should also be noticed that when MS-DOS runs in real mode, bit A20 emitted by the 80286 is gated off through a control bit provided by the keyboard controller, because real mode does not check that segment addressing does not roll over 1M (at least, that's my belief...). Moreover, bits A20-A23 are forced to high by the CPU during reset, even though it starts in real mode...

CLK I 1 System clock prescaled from 286 CPU: 6, 8 or 10 MHz, with a 50% duty cycle.

ResetDrv I 1 System reset signal (active high).

SD0-SD15 I/O 16 16 data lines (SD0 is LSB, SD15 is MSB).

BALE I 1 Buffered address latch enable. Used by slaves to latch LA17-LA23 when CPU is active. BALE is forced high when the CPU has relinquished bus control to an alternate bus master or during slave DMAs.

-I/OChCk O, OC (5k) 1 Activated (low) when a board detects a non-correctable system error (raises NMI on CPU).

-I/OChRdy O, OC (1k) 1 Activated (low) by a slave board to lenghten bus cycles. Sampled by the system board on falling edge of CLK (asynchronous setup). The cycle is completed 1 CLK period after -I/OChRdy has been sampled high by the system board. -I/OChRdy should not be pulled low for more than 2.5 ms.

IRQ3-IRQ7 O, OC

IRQ9-IRQ12 O, OC

IRQ14 O, OC

IRQ15 O, OC 11 Interrupt request lines. Interrupts are signalled by a positive edge (low to high) on an IRQ line. The pulse should be between 125 ns and 1 ms. IRQ lines 0, 1, 2, 8, 13 are used internally by the system board and are not available on the expansion bus. Highest to lowest priority is in the order 9, 10, 11, 12, 14, 15, 3, 4, 5, 6, 7. The reader is referred to IBM system board documentation for details on shared interrupts (pp 1-14 sqq.). If the interrupt line is never shared, it may also be left high until the interrupt reason is removed.

-IOR I/O, TSM 1 Read data from an I/O device (active low)

-IOW I/O, TSM 1 Write data to an I/O device (active low)

-SMemR I

-MemR I/O, TSM 2 Read data from a memory device (active low). -SMemR is derived inside the system board from -MemR and the decode of the low 1M of memory.

-SMemW I

-MemW I/O, TSM 2 Write data to a memory device (active low). -SMemW is derived inside the system board from -MemW and the decode of the low 1M of memory.

DRQ0-DRQ3 O

DRQ5-DRQ7 O 7 DMA request signals. DRQ0-DRQ3 are for 8-bit channels, DRQ5-DRQ7 for 16-bit channels. DRQ0 is highest priority, DRQ7 lowest priority.

-DAck0--DAck3 I

-DAck5--DAck7 I 7 DMA acknowledge signals (active low).

AEN I 1 Address enable. This is a very misleading name. This signal is activated by the system board when the internal DMA is driving the bus (but not when an alternate master has taken control or when the CPU is driving the bus).

-Refresh I/O, OC (300) 1 Indicates a memory refresh cycle. Normally driven by the system board every 15 ms, but may also be driven by an alternate master.

T/C I 1 Terminal count provides a high pulse when the terminal count for a system-board DMA channel is reached. T/C should be qualified by slave DMAs using the curently active DAck line.

SBHE I/O 1 Indicates transfer of data on the upper byte (SD8 through SD15) of the bus. Beware: SBHE is active low (i.e. SBHE low implies SD8 through SD15 is used) in spite of the name of the signal and the PC/AT system board IBM documentation.

-Master O, OC (300) 1 Asserted (low) by an alternate master to gain full control of the I/O channel after having received it's DAck. The alternate master should wait for one CLK period after asserting -Master before issuing addresses and data on the bus (buffer turnaround time ?). -Master should not be asserted for more than 15ms, or memory refresh might be impaired.

-MemCS16 O, OC (300) 1 Asserted (low) by a 16-bit slave memory device. Enables byte/word conversion logic if necessary. Also requires a default of 1 wait-state unless 0WS is also asserted.

-I/OCS16 O, OC (300) 1 Asserted (low) by a 16-bit slave I/O device. Enables byte/word conversion logic if necessary. Also requires a default of 1 wait-state unless 0WS is also asserted.

OSC I 1 High-speed clock at 14.31818 MHz (~70 ns) with 50% duty cycle.

0WS O, OC (300) 1 Asserted (low, in spite of the missing '-' ahead...) by a slave requiring zero wait-state. 0WS must be stable (i.e. synchronous) on the high-to-low transition of CLK following the command (-MemR / -MemW / -IOR / -IOW), i.e. at midpoint of the second cycle.

1.3. PC/AT I/O Channel timing and characteristics

Since there are no formal specification of the PC/AT I/O channel, the timing diagrams presented here should be taken with a grain of salt. I have tried to derive a consistent set of assumptions from the IBM PC/AT board schematics and the CHIPS PC/AT chip set.

The following points should be noted:

- The I/O channel is not a synchronous bus. There is no guarantee whatsoever that signals on the bus have a phase relationship with CLK unless explicitely specified. The following signals are (probably) synchronous with CLK or /CLK:

- 0WS must be stable at high-to-low edges of CLK (i.e. synchronous with /CLK)

- DAcki is stable on low-to-high edges of CLK

- T/C is stable on low-to-high edges of CLK

- -MemCS16 should be asserted on the low-to-high edge of CLK immediately following address setup to enable one wait-state processing. The only safe way to achieve this independently of the bus master is by generating -MemCS16 by a decoder on the address lines LA17-LA23.

- -I/OCS16 should be asserted on the low-to-high edge of CLK immediately following address setup to enable one wait-state processing. The only safe way to achieve this independently of the bus master is by generating -MemCS16 by a decoder on the address lines LA17-LA23.

- The timings of the bus are effectively provided by the command signals: -MemR / -MemW / -IOR / -IOW. The following timings may be safely assumed:

- SA0-SA19 are stable 15 ns before a command is asserted

- LA17-LA23 are stable 50 ns before a command is asserted

- SD0-SD15 must be valid slightly before and after (15 ns) the trailing edge of a MemR/IOR command

- -I/OCS16 should be stable as long as -IOR / -IOW is asserted (not strictly mandatory, but safer)

- SD0-SD15 are valid when a MemW/IOW command is asserted and may be removed after (15ns) the command is rescinded

- BALE is pulsed only when the system board CPU is the bus master. When an alternate master controls the bus, BALE is forced high by the system board. This implies that BALE is not a "start-cycle" signal. It's only use in a slave board should be to latch LA17-LA23. It should never be used as a timing signal. Another implication is that alternate masters should hold LA17-LA23 during the whole cycle, since they may not generate BALE.

- As mentionned earlier, MS-DOS runs in real address mode. This means that the 80286 CPU in the system board always issues 0 for the 4 high address bits. Slave boards should decode the full 24 bit address, but should be addressable within the 1st Mbyte of addresses if MS-DOS usage is required.

The I/O channel defines default durations for cycles that may be overriden:

- I/O cycles (-IOR / -IOW) have 4 wait states (i.e. the command is asserted for at least 5 CLK cycles, unless -I/OCS16 is asserted by the device, in which case 1 wait state is the default.

- Memory cycles (-MemR / -MemW) have 4 wait states unless -MemCS16 is asserted by the addressed device, resulting in 1 wait state, or -MemCS16 and 0WS are asserted by the addressed device, in which case no wait states are necessary.

Finally, the system board takes in charge the reorganization of data when the currrent cycle is between a 16-bit device and an 8-bit device. A slave is considered to be a 16-bit device if it asserts -I/OCS16 or -MemCS16 when the address is set up. The type of transfer and of master is recognized according to the table:

SBHE A0 Transfer type

0 0 16-bit master word transfer

0 1 16-bit master odd byte transfer

1 0 8/16-bit master even byte transfer

1 1 8 bit master odd byte transfer

Based on that table and the type of slave, the system board takes the following actions:

Master Slave Command Type System board action

16 bit 8 bit Write Even byte No specific action

16 bit 8 bit Write Odd byte Copy SD8-SD15 to SD0-SD7 (tri-stated by the master)

16 bit 8 bit Write Word Write SD0-SD7, then re-issue cycle with same address but SA0=1 and SD0-SD7 = SD8-SD15. Warning, this is performed only when the system board is the bus controller.

16 bit 8 bit Read Even byte No specific action

16 bit 8 bit Read Odd byte Copy SD0-SD7 to SD8-SD15 (not driven by the slave)

16 bit 8 bit Read Word Read and save value on SD0-SD7, complete current cycle, issue new cycle with same address but SA0=1 and save value from SD0-SD7 to SD8-SD15 and proceed. Warning, this is performed only when the system board is the bus controller.

8 bit 16 bit Write Even byte No specific action

8 bit 16 bit Write Odd byte Copy SD0-SD7 to SD8-SD15 (not driven by the master), set SBHE to 0

8 bit 16 bit Read Even byte No specific action

8 bit 16 bit Read Odd byte Copy SD8-SD15 to SD0-SD7 (not driven by the slave), set SBHE to 0

NOTE: There is still a doubt in my mind whether the byte copying function occurs when the current bus master is not the system board. I believe it is the case, but the PC/AT schematics should be checked once more on the subject.

1.4. Slave interface

Slave boards must generate the following signals:

- -MemCS16 or -I/OCS16 or both for a 16-bit slave responding to memory or I/O commands

- -I/OChRdy for boards requiring more than the standard number of wait-states

- 0WS for boards able to work without wait-states

Slave boards must follow the following constraints:

- LA17-LA23 must be sampled by a latch gated by BALE.

- -MemCS16 or -I/OCS16 must be generated by a static decoding of address lines following the LA17-LA23 latch. This ensures stability of -I/OCS16 throughout the cycle and also guarantees that those signals are available to the system board at the right time (whatever that is...).

- -I/OChRdy must be asserted (low) if wait-states are required before the leading CLK edge following asertion of the command signal. This requirement is for the system board. Generally, slave boards should assert -I/OChRdy immediately and then release it when they are finished.

- 0WS must be asserted (low) if no wait-states are required at all before the falling CLK edge following asertion of the command signal (i.e. extremely early: a static address decoder is the only safe way to do this). -MemCS16 should always be asserted together with 0WS. 0WS should be used only for memory accesses.

- -I/OChRdy and 0WS are exclusive signals. Asserting both will lead to unpredictable results.

- All address bits must be decoded, but MS-DOS runs in real address mode and thus generates addresses that always lie in the [0..1Mb) range.

1.5. Slave DMA interface

Slave DMA boards have the same basic interface as slave boards. In addition, they must assert a DRQi line when they require service, present or accept data when the corresponding -DAcki line becomes active (low) together with AEN and either -IOR or -IOW (depending on the transfer direction). It should be noticed that this is the only case where transfers are not conditionned by a command and an address decode.

1.6. Master interface

A master DMA board on the I/O channel has two activities: taking/releasing the bus, and generating cycles on the bus.

Taking control of the bus is achieved as follows:

1. Assert a DRQi line

2. Wait for -DAcki to be asserted (low)

3. Assert -Master (low)

The bus may effectively be used by the master board 1 CLK period after -Master has been asserted, or when AEN has been rescinded (AEN goes high when -DAcki is asserted, then goes low when -Master is asserted).

Releasing the bus is simply achieved by rescinding DRQi & -Master. A master board should avoid asserting -Master for more than 15 ms since memory refresh may not be performed while the system board is not in control of the I/O channel.

When the master has control of the bus, he must drive the following lines to generate valid cycles:

- SA0-SA19 and LA17-LA23 must be driven before a command is issued and must remain stable until after the end of the command.

- One of the command lines (-IOR / -IOW / -MemR / -MemW) must be asserted (low) to indicate a cycle. They must be kept active for a sufficiently long time as described in the following paragraph.

- SD0-SD15 must be kept stable for the whole duration of a write cycle (-IOW / -MemW).

- SD0-SD15 should be sampled on the trailing edge of a read command.

The master must generate cycles of adequate length for the slaves it controls. As mentionned above, the default timings are 4 CLK periods. A master must lenghten the cycle as long as -I/OChRdy is kept low after those minimums. A master may produce shorter cycles if the addressed slave asserts 0WS (low), requesting no wait-state, or -I/OCS16 (low), requesting only 1 wait-state for an I/O cycle, or -MemCS16 (low), requesting only 1 wait-state for a memory cycle.

1.7. Current mysteries of the PC/AT I/O channel

I still lack correct understanding of the following features and characteristics of the PC bus:

1. Word transfers between 16-bit master and 8-bit slave. If I am not mistaken, the byte swapping occurs whatever the master, but word to byte conversions occur only when the system board (CPU or DMA) is the bus master.

2. The exact timing constraints of -MemCS16 and -I/OCS16 are still a mystery insofar as the constraints are not the same for the two uses of these signals, wait-state generation (only when the system board is master, must be synchronous with CLK) and the control of the bus conversion logic (which occurs whatever the master and should not have to be synchronous).

3. SBHE appearently has no pull-up. What happens when an 8-bit device is the bus master? This is appearently prohibited.

2. IOBus definition

2.1. General comments

The IOBus is designed to be connected to a PC/AT I/O channel with a private extension to support 32-bit addressing.

Extended addressing is supported exclusively by a single IOBridge in a PC bus. It is activated by two special read/write command lines.

2.2. Pin definition

The following table indicates all the pins used with extended addressing and decoded master control:

Slave Master Size Comments

D15-D0 D15-D0 16 Data lines. Direction depends on master/slave mode and current command (read/write).

A23-A0 A23-A0 24 Low order address lines. Slave mode input, master mode output.

A31 nDEN 1 High order address line input in slave mode, data transmission enable output (active low) in master mode.

A30 DTnR 1 High order address line input in slave mode, data transmission direction output in master mode.

A29 nINTA 1 High order address line input in slave mode, interrupt acknowledge pulse output in master mode.

A28-A24 N.C. 5 High order address lines. Slave mode input, ignored in master mode.

nBHE nBHE 1 Bus high byte enable. Slave mode input, master mode output.

nReady nReady 1 Asynchronous wait signal. Slave mode output, master mode input.

nRD nRD 1 Memory read pulse. Slave mode input, master mode output.

nWR nWR 1 Memory write pulse. Slave mode input, master mode output.

nRDX nIOR 1 Extended address read pulse input in slave mode, I/O read pulse output in master mode.

nWRX nIOW 1 Extended address write pulse input in slave mode, I/O write pulse output in master mode.

nMemCS N.C. 1 Valid memory access decoded input in slave mode, ignored in master mode

nIOCS N.C. 1 I/O selection decoded input in slave and master mode. NOTE: This input may be asserted even when the IOB is master to allow self-addressing so that IOBridge I/O registers accessible from the PC side are also visible from the DynaBus.

PCLK PCLK 1 PC bus clock input. Used only in master mode so that correct timings are generated whatever the DynaBus clock period. Also used as basic timing clock for the DynaBus timers.

BReq BReq 1 Bus request signal output.

BAck BAck 1 Bus acknowledge signal input.

INTR INTR 1 Interrupt summary request input.

ITOut ITOut 1 Interrupt output to PC/AT bus (controlled by DynaBus).

nFault nFault 1 Asserted (low) when a fault is detected. Should also reflect ErrorOut from DynaBus.

Reset Reset 1 Master reset, input.

This interface provides a grand total of 63 pins. This solution offers the following advantages:

- Master cycles have a decent timing whatever the relative speed of DynaBus and PC bus clocks.

- Pin-count is reasonable.

There is a price to pay:

- IOB needs to have automata running at PCLK frequency that will be hard to test.

- The dependency of the IOBridge on the PC bus is fairly high.

- The amount of external logic is large (includes PALs and 8529A's to handle interrupts).

2.3. Timings and clarifications

The timings of the IOBus are completely asynchronous and follow exactly the specs (!) of the PC/AT I/O channel. The only signaals that are synchronous with the PC clock are the BReq/BAck signals. Actually, signals generated when the IOBridge is the bus master are also derived from the PC clock.

The IOBridge internal peripherals are memory mapped and are selected through /IOCS, whereas /MemCS indicates that a real memory cycle (with the DynaBus) is to occur. Due to the peculiarities of the PC/AT I/O channel addressing philosophy, the IOBridge has to implement some address mapping. Refer to the IOBridge specification for details of address mapping.

3. IOBridge application notes

3.1. Minimum application

The minimum application of the IOBridge consists of an IOBridge chip and two 8259A's (interrupt controllers) connected to the PC/AT I/O channel extended as described above. There are two variants for the minimum application, depending on whether the 8259A's are connected on the same side of the bus buffers as the IOBridge or have their own bus buffers. Although the first technique saves one or two chips (the data buffer and possibly the 8259A address decoding PAL), the second solution will be presented here for the sake of simplicity. Section 3.3 describes the connection of the interrupt controllers (8259A's) and optional DBus controller as a separate item. The minimum application required for the IOBridge (on the PC I/O channel side) is described in the following figure, excluding interrupt and DBus management.

[Artwork node; type 'ArtworkInterpress on' to command tool]

Minimum IOBridge application schematic

A few variations on that application are possible:

- replace the three 245A address transceivers by two 29861 and a PAL

- integrate the interrupt and DBus controller logic within the same schematic

3.2. PAL programming for minimum application

Signals that have the same name on the IOB and the PC I/O channel are indexed by PC to distinguish the two versions.

3.2.1. AddrPAL: Address decoding for the IOBridge.

AddrPAL is a PAL22V10. It generates chip select signals for the IOBridge and the remainder of the logic. It has the following inputs and outputs:

- Inputs:

- A23-A9: 16 high address lines from PC bus

- /MemRX: extended addressing memory read pulse from PC (active low)

- /MemWX: extended addressing memory write pulse from PC (active low)

- Outputs:

- /MemCS: select IOBridge as slave for an acceess to the DynaBus memory within the 24-bit addressing range

- /IOCS: select IOBridge as slave for an acceess to its internal registers

- /SlaveCS: a chip on the IOBridge side of the buffers is currently selected

NOTE: Normally, SlaveCS = MemCS + IOCS + extended addressing mode, but it may be more complex if the 8259A's are connected directly on the IOBridge side.

- /MemCS16: PC signal indicating the currently addressed device is a 16-bit slave

NOTE: /MemCS16 is obtained by enabling a TS inverter with input high by MemCS+IOCS.

The IOBridge is decoded as memory in four different memory areas:

- Part of the address range 768K-896K (3/4 to 7/8 of 1M, all other addresses below 1M are already used in the PC/AT), in steps of 16K, is used to map a 20-bit address (MSDOS runs in real address mode) into DynaBus memory through an address mapper by steps of 16K located inside the IOBridge. Up to 8 slices of 16K may be available, but one has to be set apart for access to the IOB registers (which are memory mapped) and others may have to be set apart to allow other memory-mapped I/O devices. This address range contributes to /MemCS.

- Part of a 16K byte slice in the area 768K-896K is reserved for access to the internal registers of the IOBridge. This slice should be made as small as possible (address space is scarce below 1M on the PC/AT). The size of the slice is mostly dictated by the number of address bits available for decoding. This address range results in /IOCS.

- Part of the address range 1M-15M, in steps of 1M, is used to map a 24-bit address (PC/AT in virtual mode, Ethernet controller) into DynaBus memory through an address mapper by steps of 1M located inside the IOBridge. Addresses below 1M and above 15M should never be decoded (below 1M is 20-bit addressing, above 15M is ROM area). Up to 14 slices of 1M may be decoded. This address range contributes to /MemCS.

- The whole 32-bit address space is accessible through the extended read/write pulses and contributes to SlaveCS.

The following set of equations describe the decoding logic with the following assumptions:

- 4 16-K slices (numbers 4, 5, 6, 7)

- 8 1M slices (numbers 4, 5, 6, 7, 8, 9, 10, 11)

- I/O area is lowest 512-byte range of 16-K slice number 0

The equations are then:

MemCS = /A23*/A22*/A21*/A20*A19*A18*/A17*A16 +/A23*A22 + A23*/A22 ;

IOCS = /A23*/A22*/A21*/A20*A19*A18*/A17*/A16*/A15*/A14*/A13*/A12*/A11*/A10*/A9*/A8 ;

SlaveCS = /A23*/A22*/A21*/A20*A19*A18*/A17*A16 +/A23*A22 + A23*/A22 + /A23*/A22*/A21*/A20*A19*A18*/A17*/A16*/A15*/A14*/A13*/A12*/A11*/A10*/A9 + MemRX + MemWX ;

/MemCS16 =/SlaveCS; ENABLE /MemCS16 = SlaveCS;

Drive MemCS16 only when required, otherwise float (pull-up in system board).

These equations fit inside a PAL20L8 and provide an I/O selection granularity of 512 bytes. %12 bytes is the minimum granularity for the IOBridge I/O selection.

3.2.2. BusCtlPAL: Bus allocation

BusCtlPAL is a PAL22V10 or equivalent. It converts bus requests from the IOBridge to the PC/AT I/O channel conventions. It also works as a transceiver for a few other signals. It has the following inputs and outputs:

- Inputs:

- BReq: Bus request signal from IOBridge

- /DAck: Bus grant signal from PC I/O channel

- Reset: Reset signal from PC I/O channel

- /IOR: I/O read pulse from IOBridge

- /IOW: I/O write pulse from IOBridge

- /INTA: Interrupt acknowledge pulse from IOBridge

- /Fault: Error output from IOBridge

- /MemCS16: 16-bit memory device selected, from PC (1 wait state only)

- /IOCS16: 16-bit I/O device selected, from PC (1 wait state only)

- Outputs:

- BAck: Bus grant signal to IOBridge

- DRQ: Bus request signal to PC I/O channel

- /Master : Bus mastership signal to PC I/O channel

NOTE: /Master is asserted by pulling the bus line to ground through a passing tri-state gate, and deasserted by disabling this tri-state gate. This is how the PC bus does open-collector signals...

- EnIOBM : Enable signal for bus drivers when IOBridge is bus master.

- EnPCM : Enable signal for bus drivers when PC I/O channel is bus master.

NOTE: EnIOBM and EnPCM are non-overlapping to allow for buffer turnaround time and avoid temporary shorts that might be damaging.

- /IORPC : I/O read pulse to PC

- /IOWPC : I/O write pulse to PC

- /INTA8259A : Interrupt acknowledge pulse to interrupt controllers.

- /IOChCk : Non-correctable system error line to PC

The following figure describes the timing signals that should be generated by the bus control logic:

[Artwork node; type 'ArtworkInterpress on' to command tool]

Timing of bus allocation/release automaton

The bus control logic is implemented with a 4 state automaton. This automaton guarantees that if the IOB reissues BReq before a previous DAck has been rescinded by the PC, there will be at least a one-cycle idle cycle before the bus is required again. The automaton is described by:

$Idle: IOBridge is not in a bus master sequence (initial state)

No outputs asserted

Reset => $Idle

BReq*/Reset => $WaitGrant

$WaitGrant: IOBridge waiting DAck from PC

Assert Drq

Reset => $Idle

/DAck*/Reset => $WaitGrant

DAck*/Reset => $Master

$Master: IOBridge is PC I/O channel master

Assert Drq, BAck, Master

Reset => $Idle

BReq*/Reset => $Master

/BReq*/Reset => $WaitRelease

$WaitRelease: IOBridge is requesting to release the PC I/O channel

Reset + /DAck => $Idle

DAck*/Reset => $WaitRelease

We may encode the state on 2 bits (SDAck, DRQ) so that the DRQ output is already one of the state flip-flops (SDack is a registered version of DAck):

(0,0) : $Idle

(0,1): $WaitGrant

(1,1): $Master

(1,0): $WaitRelease

After reduction, the equations for the two state flip-flops are:

SDack ← (DRQ*DAck + SDack*DRQ + SDack*DAck) * /Reset;

DRQ ← (DRQ*BReq + /SDack*DRQ + /SDack*BReq) * /Reset;

The other outputs related to bus ownership are registered to avoid glitches and are defined by the equations:

BAck ← DRQ * (/SDack*DAck + SDack*BReq) * /Reset;

A non-registered version is simply BAck = SDAck * DRQ * /Reset

Master = BAck; ENABLE Master = BAck;

Drive the pseudo open-collector signal low when bus mastership is required, else float (pull-up on system board).

EnIOBM ← BReq*SDAck*/Reset;

Delay enable by one cycle when becoming master, but cancel it immediately when releasing the bus.

EnPCM ← /DAck + /DRQ + Reset;

PC is master except if IOB requested bus and bus has been granted

NOTE: Instead of using Reset in the equations, it is also possible to use the flip-flop reset lines in the PAL if they offer the right choices of output polarity at reset time.

Finally, the remaining 5 outputs are described by:

INTA8259A = EnIOBM*INTA;

IORPC = EnIOBM*IOR;

IOWPC = EnIOBM*IOW;

The /INTA, /IOR, /IOW pins of the IOBridge are valid only when the IOBridge is the bus master.

IOChCk = Fault; ENABLE IOChCk = Fault;

Pull bus line down if there is a fault, float it (pull-up on system board) else.

3.2.3. BufferCtlPAL: buffers control

BufferCtlPAL is a PAL22V10 or equivalent. It generates the control signals for the data and address buffers between the IOBridge and the PC I/O channel, and also buffers a few additional signals. It has the following inputs and outputs:

- Inputs:

- DT/R : driven by IOBridge when master, address extension input when slave. Value is 1 to transmit data (IOB->PC), 0 to receive data (PC->IOB)

- /DEN : driven by IOBridge when master, address extension input when slave. Value is 0 to enable buffers, 1 to disable them

- /MemR : memory read pulse from PC I/O channel (active low)

- /MemW : memory write pulse from PC I/O channel (active low)

- /MemRX : memory read pulse with extended address from PC I/O channel extension (active low)

- /MemWX : memory write pulse with extended address from PC I/O channel extension (active low)

- EnIOBM : driver enable signal from bus control logic (high when IOB may drive)

- EnPCM : driver enable signal from bus control logic (high when PC may drive)

- /SlaveCS : The IOBridge side of the buffers is the currently addressed slave on the bus.

- SBHE : Data bus high byte enable (active low!) from PC Bus/IOB (slave/master)

- SA0 : Data bus low byte enable (active high!) from PC Bus/IOB (slave/master)

- Outputs:

- DXmit : 1 to transmit data from IOB to PC, 0 from PC to IOB

- /DDrvEnH : 0 to enable high-order byte data drivers, 1 to disable them

- /DDrvEnL : 0 to enable low-order byte data drivers, 1 to disable them

- AXmit : 1 to transmit addresses from IOB to PC, 0 from PC to IOB

- /RDX : extended address memory read pulse, IOB side (active low)

- /WRX : extended address memory write pulse, IOB side (active low)

- /Ready : End of cycle indication, IOB side (active low, input/output)

- /IOCHRdy : End of cycle indication, PC side (active low, input/output)

The outputs are described by the following equations:

DXmit = EnIOBM*DT/R + EnPCM * (MemR+MemRX);

Emit data when required if master, when reading if slave

DDrvEnH = EnIOBM*SBHE*DEN*/SlaveCS + EnPCM * SBHE * SlaveCS * (MemR+MemW+MemRX+MemWX) ;

When master, enable drivers when required except if IOB is supposed to answer

When slave, enable during commands to which the IOBridge responds

Enabling is conditionned to SBHE being active.

DDrvEnL = EnIOBM*/SA0*DEN*/SlaveCS + EnPCM * /SA0 * SlaveCS * (MemR+MemW+MemRX+MemWX) ;

When master, enable drivers when required except if IOB is supposed to answer

When slave, enable during commands to which the IOBridge responds

Enabling is conditionned to SA0 being low.

AXmit = EnIOBM;

Addresses flow from IOB to PC while IOB is enabled.

RDX = MemRX; ENABLE RDX = EnPCM;

Just a TS buffer.

WRX = MemWX; ENABLE MemWX = EnPCM;

Just a TS buffer.

IOChRdy = Ready*SlaveCS*EnPCM; ENABLE IOChRdy = EnPCM*SlaveCS;

Same as Ready when the IOBridge is the current slave.

Ready = IOChRdy*/SlaveCS*EnIOBM; ENABLE Ready = EnIOBM*/SlaveCS;

Ready is driven only when the IOB is the current bus master and is not addressing itself.

3.2.4. Additional notes and caveats

This application diagram is not guaranteed to be correct.

3.3. Interrupt management and DBus control

3.3.1 Application schematics

The following schematic describes the connection of the interrupt controllers and DBus manager to the PC/AT I/O channel independtly of the IOBridge connection, as mentionned in section 3.1.

[Artwork node; type 'ArtworkInterpress on' to command tool]

Interrupt and DBus controller schematic for IOBridge

The schematic is straightforward. The only delicate point is address decoding since I/O addresses are in short supply. The method chosen has been to take only two I/O slots in the 12-bit address space. Let a be the base address (a=0 mod 2, a coded on 12 bits). Then, the addresses allocated are:

a Master 8259A register 0 (R/W)

a+1H Master 8259A register 1 (R/W)

a+01000H Slave 8259A register 0 (R/W)

a+01001H Slave 8259A register 1 (R/W)

a+08000H DBus control register (To be defined)

It is possible to mix the two application schematics, but the gain is small (probably only the data transceiver) and does not seem worth the effort and confusion in the IOBridge application.

3.3.2 IOPAL: control of 8259A's and DBus master controller

The IOPAL controls the 8259A's in the configuration where they are directly connected to the PC/AT I/O channel as an I/O device using 4 addresses (the odd values are unused, the master decodes at the lower address, the slave at the upper address). It has the following inputs and outputs:

- Inputs:

- A15, A12-A1 : 13 I/O address lines

- /IOR : I/O read pulse from PC (active low)

- /IOW : I/O write pulse from PC (active low)

- Outputs:

- /MCS : Chip select for master 8259A (active low)

- /SCS : Chip select for slave 8259A (active low)

- /DCS : Chip select for DBus controller (active low)

- DCLK : Clock for loading data into the DBus register

- /DEN : Enable data buffer (active low)

- Dir : Direction of data buffer (low: receive data, high: transmit data)

The outputs are described by the following equations, where a denotes the unique base address decoding based on A11-A1 (it should be explicitely repeated each time it occurs):

MCS = /A15*/A12*a;

SCS = /A15*A12*a;

DCS = A15*a;

DCLK = IOW*A15*a;

DEN = (IOR+IOW) * a;

Dir = IOR;

IOPAL may be implemented with a PAL22V10.

NOTE: It should be noted that the default timing of I/Os is correct for the 8259A's, and thus there is no need to use /IOCHRdy.

3.3.3 DBusPAL: a crude DBus master controller

DBusPAL is a very simplified DBus controller implemented using PALs.

Exact definition to follow later. Major problem is that PALs are limited to 10 outputs. This means that it is not possible to implement an easily re-readable DBus controller in a single PAL. I see the following options:

- Provide parallel load of the 6 DBus control bits, but provide one read address per bit. Reading the parallel load address should provide the current serial data bit to minimize the handling of DX in the 80286.

- Implement the DBus controller using 2 PALs. Reasonably easy, details to work out.

- Use a 74ALS642 (transceiver with registers) or equivalent. There is only one problem: it does not provide a Reset input. This means that the Reset signal has to be handled somewhere else, but there is no room left in IOPAL: we would need 3 pins (ResetIn, DReset, D0 to modify it), and only one pin is available. A solution is to use more I/O space and remove the bits A15 and A12 from the decoder.

3.4. Hints for multi-IOBridge support

In order to debug the prototype of the hybrid machine, it will be necessary to support multiple IOBridge chips on a single PC/AT I/O channel. In such a configuration, there is no need to support extended addressing nor memory addressing: the only requirement is to be able to access the IOBridge's as slaves for I/O only and to allow each of them to be a PC master.

The modifications required in the application schematic and PALs to avoid replicating the full interface look reasonably simple, but I have not worked all the details yet.

To be defined

ChangeLog

Body