IOBridge Function
The IOBridge (IOB) is mostly a bridge between the DynaBus and the IOBus, a microprocessor-oriented bus used to support slow to medium speed (4-6 MBytes/sec) I/O and miscellaneous hardware in Dragon-based machines. It also includes a few special-purpose peripherals needed for debugging and for Cedar support. A Dragon machine may have multiple IOBridges in order to increase the I/O bandwidth and/or support esoteric hardware.
IOBus structure
The current implementation of the IOBridge uses the PC/AT bus almost directly. It extends the PC/AT address up to 34 bits (32 bits of DynaBus word address) to provide full DynaBus memory addressability. Both the I/O and memory address spaces are suported.
The choice of the IOBus used is relegated to a very isolated part of the chip, and may be changed quite easily, allowing to interface almost any bus up to 34 address bits and 32 data bits.
Bridge functionnality
From the DynaBus side, the IOBridge decodes part of the DynaBus I/O address space to generate requests on the IOBus memory and I/O address space. Those requests are queued into a FIFO and then sent serially sent on the IOBus. Data width of 8 and 16 bits are provided (32 bit transactions could be provided if the IOBus supported them). A portion of the address space is devoted to access some IOBridge internal registers.
From the IOBus side, I/O requests are converted to references to internal IOP registers. Memory requests are passed along to an external cache cache (the Dragon small cache) connected to the DynaBus. Transactions may be for 8 or 16 bits. The IOBus may also originate DynaBus I/O references (although slowly). When used as a memory on the IOBus, the IOBridge behaves as a one-wait state memory.
Internal peripherals
The IOBridge contains a 1MHz free-running 32-bit clock (permanent clock), a 10Hz loadable counter (time of day clock) and a 1KHz interrupt timer.
The IOBridge also contains interrupt support hardware that converts IOBus interrupts to DynaBus interrupts and allows to mask individual interrupts and direct them either to a specific Dragon or to all processors.
DBus support
Special I/O addresses on the IOBus are decoded by the IOBridge to generate DBus signals for the remainder of the machine, providing address setup, data transfer and DBus control. The IOBridge also contains a DynaBus test feature.