[_CD4_]<dragon7.0>IOBridge>IOBridge.oracle!1

IOBridge.oracle

Jean-Marc Frailong November 11, 1987 10:03:41 am PST

This file is the basic sanity check on the IOBridge at chip level.

Oracle wire description:

Output ( chip inputs ): ( DSerialIn nDReset nDFreeze DExecute DAddress DShiftCK HReset ) ( SStopIn Grant LongGrant HeaderCycleIn DataIn:64 ) ( PFault PReject PData:32 ) ( nReady nRD nWR nRDXnIOR nWRXnIOW nMemCS nIOCS Address:32 nBHE DATA:16 ) ( BAck INTR nFault )

Input ( chip outputs ): ( DBusOut ) ( SStopOut RequestOut:2 HeaderCycleOut DataOut:64 ) ( PhA PhB PCmd:4 PByteSel:4 PData:32 ) ( nReady nRD nWR nRDXnIOR nWRXnIOW nINTA DTnR nDEN Address:24 nBHE DATA:16 ) ( BReq IntOut nFault )

Reset sequence

Initial Hardware Reset

( X 0 0 0 0 0 1 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( X X X ) | ( X ) ( X X X XXXXXXXXXXXXXXXX ) ( X X X X XXXXXXXX ) ( X X X X X X X X XXXXXX X XXXX ) ( X X X ) -- HReset

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Check Idle outputs

Check Chip ID as 0101000111000000 ( 16 bits ) at address 0

Shift in address ( 0, 0, 0 )

( 0 0 0 0 1 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 0 = 0

( 0 0 0 0 1 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 0

( 0 0 0 0 1 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 0

( 0 0 0 0 1 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 1

( 0 0 0 0 1 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 2 = 0

( 0 0 0 0 1 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 2

Check data ( 0, 1, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0 )

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 0 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (1) = 1

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 1

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (2) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 2 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (3) = 1

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 3 = 1

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (4) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 4 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (5) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 5 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (6) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 6 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (7) = 1

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 7 = 1

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (8) = 1

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 8 = 1

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (9) = 1

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 1 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 9 = 1

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (10) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 10 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (11) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 11 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (12) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 12 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (13) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 13 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (14) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 14 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (15) = 0

( X 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 15 = 0

( X 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( 0 ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Next bit (0) = 0

Load Dynabus device ID as 005H ( 10 bits ) as address 1

Shift in address ( 0, 0, 1 )

( 1 0 0 0 1 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 2 = 1

( 1 0 0 0 1 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 2

Shift in data ( 0, 0, 0, 0, 0, 0, 0, 1, 0, 1 )

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 0 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 0

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 1

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 2 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 2

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 3 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 3

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 4 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 4

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 5 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 5

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 6 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 6

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 7 = 1

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 7

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 8 = 0

( 0 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 8

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 9 = 1

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 9

Load Cache Interrupt address base as 01AH ( 5 bits ) as address 2

Shift in address ( 0, 1, 0 )

( 1 0 0 0 1 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 1

( 1 0 0 0 1 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 1

Shift in data ( 1, 1, 0, 1, 0 )

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 0

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 0

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 1 = 1

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 1

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 3 = 1

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 3

Load MegaHertz divider as decimal 60 = 03CH ( 6 bits ) as address 3

Shift in address ( 0, 1, 1 )

Shift in data ( 1, 1, 1, 1, 0, 0 )

( 1 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Bit 2 = 1

( 1 0 0 0 0 1 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Load bit 2

Write SStopOut to 1, then to 0, then to 1 again (for arbiters)

Quiesce DBus, Reset still active

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Quiet...

Write SStopOut to 1 (address=07 internal, byte 0 MSB = byte @ 1F)

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Setup

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Initiate WR

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( X 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait end

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Ready

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- End WR

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Un-setup

Write SStopOut to 0 (address=07 internal, byte 0 MSB = byte @ 1F)

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Setup

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Initiate WR

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait end

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Ready

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- End WR

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Un-setup

Write SStopOut to 1 (address=07 internal, byte 0 MSB = byte @ 1F); arbiters synchronize on this edge of SStop

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Setup

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Initiate WR

( 0 0 0 0 0 0 0 ) ( X X X X XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait end

( 0 0 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 8000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- End WR

( 0 0 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Un-setup

Remove DReset, then SStopOut, then DFreeze: reset sequence complete

Set DynaBus input idle, then remove DReset

( 0 0 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait a bit

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- No DReset

Write SStopOut to 0 (address=07 internal, byte 0 MSB = byte @ 1F), enables arbiters

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Setup

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Initiate WR

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 1 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait end

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 0 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Ready

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XX00001F 0 0000 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- End WR

( 0 1 0 0 0 0 0 ) ( X 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 1 1 1 1 1 0 XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Un-setup

Remove DFreeze and wait a few cycles for all to be OK

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Reset done

Test DynaBus slave part

Issue IOReadRequest from DynaBus to IOBus (memory half-word read) immediately followed a series of register accesses, including IT's, followed by Dy->IOB 2-word byte-order write

Push a series of requests: IOBusRead, IORead TODC, error IOWrite ITReason, IOWrite ITReason, IOWrite ITMask, IOWrite Timer1, BIOWrite ITAck, IOBusWrite

IOReadRq IOBus 16-bits half-word order @ 123456

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 8013800035123456 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

IOReadRq TODC

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 8027000002540000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

IOWriteRq ITReason in slave mode, will reject

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9435000002540005 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 123456789ABCDEF0 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data (X)

IOWriteRq ITReason in master mode, will accept

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9035000002540005 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000BA7E0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

IOWriteRq ITMask to allow external interrupts, accept BReq

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9035000002540004 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000080000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

IOWriteRq Timer0 to 0 (initialization), accept BReq

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9035000002540001 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Data

BIOWriteRq ITAck to clear garbage

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 A035000002540003 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Header, BAck

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000060000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Data

BIOWriteRq ITMask to allow all interrupts, initiate BAck

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 A035000002540004 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000E0000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Data

IOWriteRq IOBus 32-bits in byte order, keep BAck

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9013800045ABCDE3 ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Header, check IOBus addr, force nIOCS/nMemCS

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 02468ACE13579BDF ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Data

Complete IOBus master read cycle

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- check IOBus addr, force nIOCS/nMemCS

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- nRD

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- nRD on 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( 1 X X X X 1 1 XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- nRD on 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( 1 X X X X 1 1 XXXXXXXX X ABCD ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- Setup data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( 1 X X X X 1 1 XXXXXXXX X ABCD ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 123456 0 XXXX ) ( 1 0 1 ) -- End of nRD

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( 1 X X X X X X XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- End of BReq, deassert nIOCS, nMemCS

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( 1 X X X X X X XXXXXXXX X XXXX ) ( 1 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Last BAck

IOReadRply IOBus

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Rqst 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Rqst 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 3 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Accept Rqst

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Grant 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Grant 2

( 0 1 1 0 0 0 0 ) ( 0 0 0 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- GLength

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant1

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 1 8813800035123456 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 0 000000000000ABCD ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle

IOReadReply TODC

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 1 8827000002540000 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 0 XXXXXXXX00000005 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

IOWriteReply TODC, in error (data is error, MSW not significative)

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 1 9C35000002540005 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 0 XXXXXXXX0140000B ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

IOWriteReply ITReason, initiate IOBus interrupt for later processing

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Grant 1, start IOBus interrupt

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Grant 2

( 0 1 1 0 0 0 0 ) ( 0 0 0 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- GLength

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant1

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 9835000002540005 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 0 XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle

IOWriteReply ITMask

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 3 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Accept Rqst

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Wait Grant 1

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 9835000002540004 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 0 XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data (X)

IOWriteReply Timer1

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 9835000002540001 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

IOWriteRequest Interrupt & corresponding reply

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 940280000019F81A ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 0 0000000000000100 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data (X)

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 9C0280000019F81A ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Reply Hdr

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Reply Data

Internal delays (to be checked)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 6

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 7

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 8

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 9

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 10

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 11

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Delay 12

Accept master 32-bit write to IOBus

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- BReq

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- Wait

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- BAck 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- BAck 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE2 0 XXXX ) ( 1 0 1 ) -- BAck 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE2 0 XXXX ) ( 1 0 1 ) -- BAck 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- BAck 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- nWR 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE2 0 DF9B ) ( 1 0 1 ) -- nWR Off 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 1 0 1 ) -- nWR Off 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE0 0 XXXX ) ( 1 0 1 ) -- nWR Off 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR Off 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 1 XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X ABCDE0 0 5713 ) ( 1 0 1 ) -- nWR Off

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- BReq Off

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 1 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- remove BAck

IOWriteReply IOBus 32-bit write, terminate BAck from previousIOBus cycle

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 9813800045ABCDE3 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

Issue a series of BIOWrites to try to saturate the input FIFO

BIOWrite Timer 1 with 00000000

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 A035000002540001 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000000000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00010000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000010000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00030000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000030000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00040000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000040000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00050000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000050000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00060000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000060000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00070000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000070000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00080000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000080000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00090000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000090000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000A0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000A0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000B0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000B0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000C0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000C0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000D0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000D0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000E0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000E0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 000F0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000000F0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00100000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000100000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00110000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000110000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00120000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000120000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00130000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000130000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00140000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000140000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00150000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000150000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00160000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000160000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00170000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000170000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00180000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000180000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00190000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000190000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001A0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001A0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001B0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001B0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001C0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001C0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001D0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001D0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001E0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001E0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 001F0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000001F0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00200000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000200000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00210000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000210000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00220000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000220000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00230000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000230000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00240000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000240000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00250000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000250000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00260000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000260000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00270000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000270000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00280000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000280000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 00290000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 0000000000290000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 002A0000

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000002A0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

BIOWrite Timer 1 with 002B0000 -- this one should get lost in the battle...

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 00000000002B0000 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

Wait a few cycles, then issue IOReadRqst for Timer 1 to check the value is 002Axxxx

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 1 8027000002540001 ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Header

Wait for the IOReadRqst to proceed to the request stage

IOReadReply Timer1 (it took a long time to get there...)

( 0 1 1 0 0 0 0 ) ( 0 1 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 1 8827000002540001 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Grant2 header

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 1 X ) | ( X ) ( 0 0 0 00000000002A0000 ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Data

Test of the IOBus slave part

Read well-known values

Read DynaBus Device ID (nIOCS @ 1A)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- Setup

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- nRD=>nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- nRD1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- nRD2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- nRD3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 00001A 0 0005 ) ( 0 0 1 ) -- nRD4=>Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 00001A 0 0005 ) ( 0 0 1 ) -- Wait 0

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 00001A 0 0005 ) ( 0 0 1 ) -- Wait 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 00001A 0 0005 ) ( 0 0 1 ) -- Wait 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000001A 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00001A 0 XXXX ) ( 0 0 1 ) -- End nRD

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Un-setup

Regular PBus access for read through large map

Setup large map entry #3, write 16 addr MSB in MSB half of entry...

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000008E 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00008E 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000008E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00008E 0 1234 ) ( 0 0 1 ) -- End nWR

Read memory word at addr 003ABCDE

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- Setup

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- nRD=>nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- nRD 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- nRD 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 8 3 1236AF37 ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- PhA

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 8 3 XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- PhA end (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 8 3 XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- PhB

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 0 0 12345678 ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- PhB reply

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- End PBus

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 3ABCDE 0 7856 ) ( 0 0 1 ) -- Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 3ABCDE 0 7856 ) ( 0 0 1 ) -- nRD

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 0 1 003ABCDE 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 3ABCDE 0 XXXX ) ( 0 0 1 ) -- End nRD

Read explicitely the PBus output register, should result in opposite byte order

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- Setup

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- nRD => nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- nRD1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- nRD2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- nRD3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000008 0 5678 ) ( 0 0 1 ) -- nRD4=>Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000008 0 5678 ) ( 0 0 1 ) -- Wait 0

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000008 0 5678 ) ( 0 0 1 ) -- Wait 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000008 0 5678 ) ( 0 0 1 ) -- Wait 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000008 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000008 0 XXXX ) ( 0 0 1 ) -- End nRD

Regular PBus access write through small map with one reject cycle

Setup small map entry #B, write 16 addr MSB in MSB half of entry...

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006E 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006E 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006E 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006E 0 1234 ) ( 0 0 1 ) -- End nWR

Setup small map entry #B, write 16 addr LSB in LSB half of entry...

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006C 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006C 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000006C 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00006C 0 5678 ) ( 0 0 1 ) -- End nWR

Write memory byte at logical addr 0000B123

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 0 1 0000B123 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00B123 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- Setup D

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- nWR, nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 9 1 12345448 ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- PhA1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 9 1 XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- PhA2 (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 9 1 XXXXXX24 ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- PhB1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 0 1 XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXX24 ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- PhB2 with Reject

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- PhB3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 0 0 12345448 ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- 2nd PhA1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- 2nd PhA2 (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- 2nd PhB1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 0 0 XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- 2nd PhB2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- End PBus

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- nWR

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 0 1 0000B123 0 2468 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00B123 0 2468 ) ( 0 0 1 ) -- End nWR

Do a programmed access: write 13579BDF @ 12345678, then same programmed read with a fault

Write PBus addr register (low 2 bytes : 5678)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000004 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000004 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000004 0 5678 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000004 0 5678 ) ( 0 0 1 ) -- End nWR

Write PBus addr register (high 2 bytes : 1234)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000006 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000006 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000006 0 1234 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000006 0 1234 ) ( 0 0 1 ) -- End nWR

Write PBus data register (low 2 bytes : 9BDF)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000000 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000000 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000000 0 9BDF ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000000 0 9BDF ) ( 0 0 1 ) -- End nWR

Write PBus data register (high 2 bytes : 1357)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000002 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000002 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR=>nRdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR4=>Rdy

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000002 0 1357 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000002 0 1357 ) ( 0 0 1 ) -- End nWR

Write command register with PCmd=E1, a write command

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000000C 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00000C 0 XXXX ) ( 0 0 1 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR, nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 9 C 12345678 ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- PhA1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 9 C XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- PhA2 (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 9 C 13579BDF ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- PhB1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 0 0 XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 13579BDF ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- PhB2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- PBus done

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR4, Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000000C 0 00E1 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00000C 0 00E1 ) ( 0 0 1 ) -- End nWR

Write command register with PCmd=98, a read command and get a fault

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- nWR, nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- nWR 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 8 3 12345678 ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- PhA1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 8 3 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- PhA2 (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 8 3 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- PhB1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 1 1 XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- PhB2 , Reject & Fault

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 1 ) -- PhB3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 1 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- 2nd PhA1, nFault appears (until cleared explicitly)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- 2nd PhA2 (invisible due to clock skews...)

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- 2nd PhB1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( 0 0 XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 1 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- 2nd PhB2, neither Reject nor fault

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 0 0 XXXXXXXX ) ( 0 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- PBus done

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- nWR4, Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 0000000C 0 0098 ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 00000C 0 0098 ) ( 0 0 0 ) -- End nWR

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 0 ) -- Un-setup

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 0 ) -- Idle

Read MSB of PBus error address register to check address fault logged

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- Setup

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- nRD=>nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- nRD1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- nRD2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 0 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- nRD3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000016 0 1234 ) ( 0 0 0 ) -- nRD4=>Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000016 0 1234 ) ( 0 0 0 ) -- Wait 0

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000016 0 1234 ) ( 0 0 0 ) -- Wait 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X 0 X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 0 1 1 1 X X X 000016 0 1234 ) ( 0 0 0 ) -- Wait 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000016 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000016 0 XXXX ) ( 0 0 0 ) -- End nRD

Write PBusFault register (byte @ 19) to clear nFault. Data may be random

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000019 0 XXXX ) ( 0 0 0 ) -- Setup @

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000019 0 XXXX ) ( 0 0 0 ) -- Setup Data

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 0 ) -- nWR, nReady

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 0 ) -- nWR 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 0 ) -- nWR 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 0 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 1 ) -- nWR 3, nFault removed

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 1 ) -- Ready

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X 0 X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 0 1 1 X X X 000019 0 XXXX ) ( 0 0 1 ) -- nWR 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X 1 0 00000019 0 XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X 000019 0 XXXX ) ( 0 0 1 ) -- End nWR

End of simulation

Idle cycles to see the future...

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 1

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 2

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 3

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 4

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 5

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 6

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 7

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 8

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 9

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 10

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 11

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 12

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 13

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 14

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 15

( 0 1 1 0 0 0 0 ) ( 0 0 X 0 XXXXXXXXXXXXXXXX ) ( X X XXXXXXXX ) ( X X X X X X X XXXXXXXX X XXXX ) ( 0 0 X ) | ( X ) ( 0 0 X XXXXXXXXXXXXXXXX ) ( 0 0 X X XXXXXXXX ) ( 1 1 1 1 1 X X X XXXXXX X XXXX ) ( 0 0 1 ) -- Idle 16

. -- END OF SIMULATION