[_CD4_]<dragon7.0>IOBridge>IOBTimingRegs.oracle!1

IOBTimingRegs.oracle

Jean-Marc Frailong April 21, 1987 6:39:40 pm PDT

This test file assumes that the prescaler counter has been set up to divide by 8 so as to reduce the length of the test...

Outputs:

RefClock (0), Reset (0), WTmr1 (0), WTmr2 (0), DIn (32)

Inputs:

Tmr1Int (0), Tmr2Int (0), FCkOut (32), Tmr1Out (32), Tmr2Out (32)

RefClock Reset WTmr1 WTmr2 DIn | Tmr1Int Tmr2Int FCkOut Tmr1Out Tmr2Out -- Comment

Reset sequence, pre-fill RefClock pipeline

0 1 1 1 00000000 | X X XXXXXXXX XXXXXXXX XXXXXXXX -- First reset

1 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check FCkOut is reset

0 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check RefClock is ineffective

1 1 0 0 XXXXXXXX | 0 0 00000000 00000000 00000000 -- Check RefClock is ineffective

Check that the other timers do get written into correctly and test the first step of FCk

0 0 1 0 01234567 | 0 0 00000000 XXXXXXXX XXXXXXXX -- Tmr1 ← 01234567

1 0 0 1 89ABCDEF | 0 0 00000000 01234567 XXXXXXXX -- Tmr2 ← 89ABCDEF, check Tmr1

0 0 1 0 FFFFFFFE | 0 0 00000000 01234567 89ABCDEF -- Tmr1 ← FFFFFFFE, check Tmr2

1 0 0 1 01234567 | 0 0 00000000 FFFFFFFE 89ABCDEF -- Tmr2 ← 01234567, check Tmr1

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← A, check Tmr2

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← B

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← C

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← D

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← E

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- MHz ← F

1 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567

0 0 0 0 XXXXXXXX | 0 0 00000000 FFFFFFFE 01234567 -- SCk1MHz ← 1

One step of all counters, Tmr1Int gets raised

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- counters +𡤁

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← 9

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← A

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← B

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← C

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← D

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← E

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568 -- MHz ← F

1 0 0 0 XXXXXXXX | 0 0 00000001 FFFFFFFF 01234568

0 0 0 0 XXXXXXXX | 1 0 00000001 FFFFFFFF 01234568 -- SCk1MHz ← 1

One step of all counters, reload Tmr2 just before it gets incremented

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- counters +𡤁

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← 9

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← A

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← B

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← C

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← D

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← E

1 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 01234569 -- MHz ← F

1 0 0 1 FFFFFFFE | 0 0 00000002 00000000 01234569

0 0 0 0 XXXXXXXX | 0 0 00000002 00000000 FFFFFFFE -- SCk1MHz ← 1

One step of all counters, Tmr2 is not updated

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- counters +𡤁

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← 9

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← A

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← B

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← C

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← D

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← E

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- MHz ← F

1 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE

0 0 0 0 XXXXXXXX | 0 0 00000003 00000001 FFFFFFFE -- SCk1MHz ← 1

One step of all counters, Tmr2 is updated this time and creates an interrupt

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- counters +𡤁

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← 9

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← A

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← B

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← C

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← D

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← E

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF -- MHz ← F

1 0 0 0 XXXXXXXX | 0 0 00000004 00000002 FFFFFFFF

0 0 0 0 XXXXXXXX | 0 1 00000004 00000002 FFFFFFFF -- SCk1MHz ← 1

One step of all counters, nothing happens

1 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- counters +𡤁

0 0 0 0 XXXXXXXX | 0 0 00000005 00000003 00000000 -- MHz ← 9