[_CD4_]<dragon7.0>IOBridge>IOBPinOut.tioga!1

IOBRIDGE PIN COUNT

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

IOBRidge pin count

Subtitle, if any

Jean-Marc Frailong

Dragon-86-xx Written January 27, 1987 Revised Month, Year

Abstract: This document describes the current status of the pin-out of the IOBridge chip.

Keywords: June87, IOBridge

FileName: IOBPinOut.tioga, .interpress

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

Dragon Project - For Internal Xerox Use Only

Contents

1. DynaBus interface

2. DBus interface

3. PBus interface

4. IOBus interface

Appendix A. Appendix A Title

Appendix B. Appendix B Title

ChangeLog

1. DynaBus interface

1.1 List of pins

The list of pins used for the DynaBus interface in the IOBridge is as follows:

Name Size Direction Comments

Clock 1 I

DataOut 64 O

HeaderCycleOut 1 O

ParityOut 1 O

DataIn 64 I

HeaderCycleIn 1 I

ParityIn 1 I

GrantIn 1 I

PriorityIn 1 I

SharedIn 1 I Not required

OwnerIn 1 I Not required

ErrorIn 1 I

RequestOut 1 O

PriorityOut 1 O

SharedOut 1 O Not required

OwnerOut 1 O Not required

ErrorOut 1 O

This list is directly derived from DynaHInterface.icon and ClockInterface.icon in DynaHInterface.dale.

The total number of pins required is thus 143. 4 pins might be easily removed, leading to a total of 139 pins.

1.2 Possible reductions

There are no possible reductions in size of the DynaBus interface except for the 4 pins mentionned above.

2. DBus interface

2.1 List of pins

The list of pins used for the slave DBus interface in the IOBridge is as follows:

Name Size Direction Comments

DSerialOut 1 O

DSerialIn 1 I

DShiftCK 1 I

DAddress 1 I

DExecute 1 I

DFreeze 1 I

DReset 1 I

DSelect 1 I

The list of pins used for the (optional) master DBus interface in the IOBridge is as follows:

Name Size Direction Comments

DMSerialOut 1 O

DMSerialIn 1 I

DMShiftCKOut 1 O May be shared with DBus slave

DMAddressOut 1 O May be shared with DBus slave

DMExecuteOut 1 O May be shared with DBus slave

DMFreezeOut 1 I May be shared with DBus slave

DMResetOut 1 O May be shared with DBus slave

The total number of pins required is thus 8 for the slave DBus and 7 for thee optional master DBus.

2.2 Possible reductions

If only the slave DBus is implemented, the 8 pins cannot be reduced. If the DBus master is integrated into the IOBridge, it becomes possible to share all master pins with slave pins except for the 2 serial data pins. Whether a given IOBridge is the DBus master or not would then be decided by programming a specific bit in the IOBridge enabling the DBus master outputs for this chip.

The net result is that it might be possible to go down to 10 pins for the DBus interface with both slave and master DBus interfaces.

3. PBus interface

3.1 List of pins

The list of pins used for the PBus interface in the IOBridge is as follows:

Name Size Direction Comments

PBusData 32 I/O

PBusCmd 8 I/O

Reject 1 I

Fault 4 I may be reduced to 1

PhA 1 O

PhB 1 O

The total number of pins required is thus 47.

3.2 Possible reductions

An obvious reduction consists in using only the fault flag bit, and dropping the fault code. Since it is kept inside the cache anyway, it may be recovered by software and the IOB does not need to make its own copy.

Thus, an obvious reduction leads to 44 pins.

4. IOBus interface

4.1 List of pins

The list of pins used for the IOBus interface in the IOBridge is as follows:

Name Size Direction Comments

D15-D0 16 I/O

A23-A0 24 I/O

A31-A24 8 I/O multiplexed with control signals

BHE 1 I/O

/Ready 1 I/O

/RD 1 I/O

/WR 1 I/O

/IOR 1 I/O multiplexed with /RDX

/IOW 1 I/O multiplexed with /WRX

/MemCS 1 I

/IOCS 1 I

PCLK 1 I PC Clock (6,8,10 MHz)

BReq 1 O

BAck 1 I

INTR 1 I Interrupt line from 8259As

/Fault 1 I PC /IOChChk

Reset 1 I

The total number of pins required is thus 62.

4.2 Possible reductions

No possible reduction in this interface

4. Grand total

We thus obtain the following estimate for the number of signal pins in the IOBridge:

Type Maximum Realistic

DynaBus 143 139

DBus 10 8

PBus 47 44

IOBus 62 62

Grand total 262 253

This table shows that the realistic estimate (which is not completely obvious to achieve) is on the border of feasibility, and that going to the absolute minimum gains only very little for a lot of sadditionnal problems. Still, I feel quite uneasy with so many signal pins.

ChangeLog

Jean-Marc Frailong March 3, 1987 12:46:39 pm PST

Updated pin counts espeecially for the IOBus and DBus sections

changes to: all