[_CD4_]<dragon7.0>IOBridge>IOBMasterDBus.oracle!1

IOBMasterDBus.oracle

Jean-Marc Frailong January 27, 1987 7:33:47 pm PST

This test file assumes that DSDFreeze is grounded, and that SDShift and SDAddr are obtained by delaying DMDShift and DMDAddr by 5 clocks.

Outputs:

Reset (0), DIn (32), nByteEn (4), WRCtl (2: WRDAddr, WRDData), DMSerialIn (0). DSDFreeze is forced to Gnd since it is not really used anyway.

Inputs:

DAddrOut (32), DDataOut (32), DMDShift (0), DMDAddr (0), DMDExecute (0), DMSerialOut (0). DMDFreeze and DMDReset are also in DAddrOut.

Reset DIn nByteEn WRCtl DMSerialIn | DAddrOut DDataOut DMDShift DMDAddr DMDExecute DMSerialOut -- Comment

Test of the IOB Debug Bus Master

Reset sequence

1 00000000 0 0 0 | XXXXXXXX XXXXXXXX X X X X -- Unknown initial state

1 00000000 0 0 0 | 00010000 00000000 0 0 0 X -- Automatic reset of all regs

1 00000000 0 0 0 | 00010000 00000000 0 0 0 X -- Wait for DMDShift/DMDAddr loop

1 00000000 0 0 0 | 00010000 00000000 0 0 0 X

1 00000000 0 0 0 | 00010000 00000000 0 0 0 0 -- DMSerialOut should be stable now

0 00000000 0 0 0 | 00010000 00000000 0 0 0 0 -- Rescind Reset

Load all registers except for command

0 FEDCBA98 F 1 0 | 00010000 00000000 0 0 0 0 -- Setup data register

0 00000000 0 0 0 | 00010000 FEDCBA98 0 0 0 1 -- Check written

0 5A010203 8 1 0 | 00010000 FEDCBA98 0 0 0 1 -- Rewrite it byte per byte

0 5A010203 4 1 0 | 00010000 5ADCBA98 0 0 0 0 -- Rewrite it byte per byte

0 5A010203 2 1 0 | 00010000 5A01BA98 0 0 0 0 -- Rewrite it byte per byte

0 5A010203 1 1 0 | 00010000 5A010298 0 0 0 0 -- Rewrite it byte per byte

0 FFFF3456 3 2 0 | 00010000 5A010203 0 0 0 0 -- Setup DBus addr register

0 04888888 8 2 0 | 00013456 5A010203 0 0 0 0 -- Setup DBus data len register

0 00020000 4 2 0 | 04013456 5A010203 0 0 0 0 -- Remove Reset, Set Freeze

0 00000000 0 0 0 | 04023456 5A010203 0 0 0 0 -- Check results

Do a Data Shift cycle

Setup command

0 001A0000 4 2 0 | 04023456 5A010203 0 0 0 0 -- Setup Data shift command

0 00000000 0 0 0 | 049A3456 5A010203 1 0 0 0 -- One pipeline delay

Bit 0 out

0 00000000 0 0 0 | 049A3456 5A010203 1 0 0 0 -- DShift (1)

0 00000000 0 0 0 | 049A3456 5A010203 1 0 0 0 -- DShift (2)

0 00000000 0 0 0 | 049A3456 5A010203 1 0 0 0 -- DShift (3)

0 00000000 0 0 0 | 049A3456 5A010203 1 0 0 0 -- DShift (4)

0 00000000 0 0 0 | 049A3456 5A010203 0 0 0 0 -- nDShift (1)

0 00000000 0 0 0 | 049A3456 B4020406 0 0 0 1 -- nDShift (2), early shift!

0 00000000 0 0 0 | 049A3456 B4020406 0 0 0 1 -- nDShift (3)

0 00000000 0 0 0 | 049A3456 B4020406 0 0 0 1 -- nDShift (4)

Bit 1 out

0 00000000 0 0 0 | 049A3456 B4020406 1 0 0 1 -- DShift (1)

0 00000000 0 0 1 | 049A3456 B4020406 1 0 0 1 -- DShift (2)

0 00000000 0 0 1 | 049A3456 B4020406 1 0 0 1 -- DShift (3)

0 00000000 0 0 1 | 049A3456 B4020406 1 0 0 1 -- DShift (4)

0 00000000 0 0 1 | 049A3456 B4020406 0 0 0 1 -- nDShift (1)

0 00000000 0 0 1 | 049A3456 B4020406 0 0 0 1 -- nDShift (2)

0 00000000 0 0 1 | 049A3456 6804080D 0 0 0 0 -- nDShift (3), do it really

0 00000000 0 0 1 | 049A3456 6804080D 0 0 0 0 -- nDShift (4)

Bit 2 out

0 00000000 0 0 1 | 049A3456 6804080D 1 0 0 0 -- DShift (1)

0 00000000 0 0 0 | 049A3456 6804080D 1 0 0 0 -- DShift (2)

0 00000000 0 0 0 | 049A3456 6804080D 1 0 0 0 -- DShift (3)

0 00000000 0 0 0 | 049A3456 6804080D 1 0 0 0 -- DShift (4)

0 00000000 0 0 0 | 049A3456 6804080D 0 0 0 0 -- nDShift (1)

0 00000000 0 0 0 | 049A3456 6804080D 0 0 0 0 -- nDShift (2)

0 00000000 0 0 0 | 049A3456 D008101A 0 0 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 049A3456 D008101A 0 0 0 1 -- nDShift (4)

Bit 3 out

0 00000000 0 0 0 | 049A3456 D008101A 1 0 0 1 -- DShift (1)

0 00000000 0 0 0 | 049A3456 D008101A 1 0 0 1 -- DShift (2)

0 00000000 0 0 0 | 049A3456 D008101A 1 0 0 1 -- DShift (3)

0 00000000 0 0 0 | 049A3456 D008101A 1 0 0 1 -- DShift (4)

0 00000000 0 0 0 | 049A3456 D008101A 0 0 0 1 -- nDShift (1)

0 00000000 0 0 0 | 049A3456 D008101A 0 0 0 1 -- nDShift (2)

0 00000000 0 0 0 | 049A3456 A0102034 0 0 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 049A3456 A0102034 0 0 0 1 -- nDShift (4)

Bit 4 out

0 00000000 0 0 0 | 049A3456 A0102034 1 0 0 1 -- DShift (1)

0 00000000 0 0 1 | 049A3456 A0102034 1 0 0 1 -- DShift (2)

0 00000000 0 0 1 | 049A3456 A0102034 1 0 0 1 -- DShift (3)

0 00000000 0 0 1 | 049A3456 A0102034 1 0 0 1 -- DShift (4)

0 00000000 0 0 1 | 049A3456 A0102034 0 0 0 1 -- nDShift (1)

0 00000000 0 0 1 | 049A3456 A0102034 0 0 0 1 -- nDShift (2)

0 00000000 0 0 1 | 049A3456 40204069 0 0 0 0 -- nDShift (3), do it really

0 00000000 0 0 1 | 049A3456 40204069 0 0 0 0 -- nDShift (4)

End of the Data shift automaton

0 00000000 0 0 1 | 04023456 40204069 0 0 0 0 -- DShift does not appear anymore

0 00000000 0 0 0 | 04023456 40204069 0 0 0 0 -- DShift does not appear anymore

Do an Address Shift cycle

Setup command

0 00120000 4 2 0 | 04023456 40204069 0 0 0 0 -- Setup Addr shift command

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- One pipeline delay

Initial DAddr phase (16 cycles)

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- DMDAddr only for 16 cycles first

Bit 0 out

0 00000000 0 0 0 | 04923456 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04923456 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04923456 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04923456 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 049268AC 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 049268AC 40204069 0 1 0 0 -- nDShift (4)

Bit 1 out

0 00000000 0 0 0 | 049268AC 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 049268AC 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 049268AC 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 049268AC 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 049268AC 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 049268AC 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 0492D158 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492D158 40204069 0 1 0 1 -- nDShift (4)

Bit 2 out

0 00000000 0 0 0 | 0492D158 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 0492D158 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 0492D158 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 0492D158 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 0492D158 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 0492D158 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 0492A2B1 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492A2B1 40204069 0 1 0 1 -- nDShift (4)

Bit 3 out

0 00000000 0 0 0 | 0492A2B1 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 0492A2B1 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 0492A2B1 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 0492A2B1 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 0492A2B1 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 0492A2B1 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 04924563 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04924563 40204069 0 1 0 0 -- nDShift (4)

Bit 4 out

0 00000000 0 0 0 | 04924563 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04924563 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04924563 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04924563 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04924563 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04924563 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 04928AC6 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 04928AC6 40204069 0 1 0 1 -- nDShift (4)

Bit 5 out

0 00000000 0 0 0 | 04928AC6 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 04928AC6 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 04928AC6 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 04928AC6 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 04928AC6 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 04928AC6 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 0492158D 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492158D 40204069 0 1 0 0 -- nDShift (4)

Bit 6 out

0 00000000 0 0 0 | 0492158D 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 0492158D 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 0492158D 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 0492158D 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 0492158D 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 0492158D 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 04922B1A 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04922B1A 40204069 0 1 0 0 -- nDShift (4)

Bit 7 out

0 00000000 0 0 0 | 04922B1A 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04922B1A 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04922B1A 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04922B1A 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04922B1A 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04922B1A 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 04925634 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04925634 40204069 0 1 0 0 -- nDShift (4)

Bit 8 out

0 00000000 0 0 0 | 04925634 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04925634 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04925634 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04925634 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04925634 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04925634 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 0492AC68 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492AC68 40204069 0 1 0 1 -- nDShift (4)

Bit 9 out

0 00000000 0 0 0 | 0492AC68 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 0492AC68 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 0492AC68 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 0492AC68 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 0492AC68 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 0492AC68 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 049258D1 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 049258D1 40204069 0 1 0 0 -- nDShift (4)

Bit 10 out

0 00000000 0 0 0 | 049258D1 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 049258D1 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 049258D1 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 049258D1 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 049258D1 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 049258D1 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 0492B1A2 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492B1A2 40204069 0 1 0 1 -- nDShift (4)

Bit 11 out

0 00000000 0 0 0 | 0492B1A2 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 0492B1A2 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 0492B1A2 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 0492B1A2 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 0492B1A2 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 0492B1A2 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 04926345 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04926345 40204069 0 1 0 0 -- nDShift (4)

Bit 12 out

0 00000000 0 0 0 | 04926345 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04926345 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04926345 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04926345 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04926345 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04926345 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 0492C68A 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 0492C68A 40204069 0 1 0 1 -- nDShift (4)

Bit 13 out

0 00000000 0 0 0 | 0492C68A 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 0492C68A 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 0492C68A 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 0492C68A 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 0492C68A 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 0492C68A 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 04928D15 40204069 0 1 0 1 -- nDShift (3), do it really

0 00000000 0 0 0 | 04928D15 40204069 0 1 0 1 -- nDShift (4)

Bit 14 out

0 00000000 0 0 0 | 04928D15 40204069 1 1 0 1 -- DShift (1)

0 00000000 0 0 0 | 04928D15 40204069 1 1 0 1 -- DShift (2)

0 00000000 0 0 0 | 04928D15 40204069 1 1 0 1 -- DShift (3)

0 00000000 0 0 0 | 04928D15 40204069 1 1 0 1 -- DShift (4)

0 00000000 0 0 0 | 04928D15 40204069 0 1 0 1 -- nDShift (1)

0 00000000 0 0 0 | 04928D15 40204069 0 1 0 1 -- nDShift (2)

0 00000000 0 0 0 | 04921A2B 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04921A2B 40204069 0 1 0 0 -- nDShift (4)

Bit 15 out

0 00000000 0 0 0 | 04921A2B 40204069 1 1 0 0 -- DShift (1)

0 00000000 0 0 0 | 04921A2B 40204069 1 1 0 0 -- DShift (2)

0 00000000 0 0 0 | 04921A2B 40204069 1 1 0 0 -- DShift (3)

0 00000000 0 0 0 | 04921A2B 40204069 1 1 0 0 -- DShift (4)

0 00000000 0 0 0 | 04921A2B 40204069 0 1 0 0 -- nDShift (1)

0 00000000 0 0 0 | 04921A2B 40204069 0 1 0 0 -- nDShift (2)

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- nDShift (3), do it really

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- nDShift (4)

Terminal DAddr phase (16 cycles)

0 00000000 0 0 0 | 04923456 40204069 0 1 0 0 -- DMDAddr only for 16 cycles last

End of the Address shift automaton

0 00000000 0 0 0 | 04023456 40204069 0 0 0 0 -- DMDAddr rescinded

Do an Execute cycle (it lasts 9 cycles instead of 8)

0 000A0000 4 2 0 | 04023456 40204069 0 0 0 0 -- Setup Execute command

0 00000000 0 0 0 | 048A3456 40204069 0 0 1 0 -- Should take 8 cycles

0 00000000 0 0 0 | 04023456 40204069 0 0 0 0 -- End of Execute

Check cycle overlap protection

0 000A0000 4 2 0 | 04023456 40204069 0 0 0 0 -- Setup Execute command

0 00000000 0 0 0 | 048A3456 40204069 0 0 1 0 -- Normal Execute cycle

0 001A0000 4 2 0 | 048A3456 40204069 0 0 1 0 -- Insert Data shift in the middle

0 00000000 0 0 0 | 048A3456 40204069 0 0 1 0 -- Nothing should change

0 00000000 0 0 0 | 048A3456 40204069 0 0 1 0 -- Normal Execute cycle

0 00000000 0 0 0 | 04023456 40204069 0 0 0 0 -- End of Execute