IOBInnerDBMaster.oracle
Jean-Marc Frailong August 5, 1987 5:28:44 pm PDT
Notes: This file assumes that the DynaBus device ID is hardwired to 005H, the cache interrupt address is 0123H, and that HReset/Reset are externally driven to last less than 12 cycles. It also assumes that the PC clock has 1/2 the DynaBus clock frequency. It tests the DynaBus slave half of the IOBridge.
Outputs:
( iHeaderIn (0), iDataIn (64), iGrant (0), iGLength (0) ), ( iPFault (0), iPReject (0), PBusIn (32) ), ( MBAck (0), MnReady (0), INT (0), nCS (2: 3 -> none, 2 -> IOCS, 1 -> MemCS, 0 -> prohibited), nSCmd (4: 7 -> WRX, B -> RDX, D -> WR, E -> RD, F -> none), IOBAddrIn (32), nBHEIn (0), IOBDataIn (16) )
Inputs:
( iHeaderOut (0), iDataOut (64), iRequest (2) ), ( iPhA (0), iPhB (0), DrvPBus (0), iPCmd (8), PBusOut (32) ), ( MBReq (0), SnReady (0), nMCmd (4: 7 -> IOW, B -> IOR, D -> WR, E -> RD, F -> none), IOBAddrOut (24), nBHEOut (0), IOBDataOut (16) )
( iHeaderIn iDataIn iGrant iGLength ) ( iPFault iPReject PBusIn ) ( MBAck MnReady INT nCS nSCmd IOBAddrIn nBHEIn IOBDataIn) | ( iHeaderOut iDataOut iRequest ) ( iPhA iPhB DrvPBus iPCmd PBusOut ) ( MBReq SnReady nMCmd IOBAddrOut nBHEOut IOBDataOut) -- Comment
Test of the IOBridge inner (DBus slave excluded)
HReset & Reset (hardwired in cell, 12 cycles)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( X XXXXXXXXXXXXXXXX X ) ( X X X XX XXXXXXXX ) ( X X X XXXXXX X XXXX ) -- Nothing
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Check all stable
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Check all stable
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Check all stable
Sanity check: read a well-known register
Read DynaBus Device ID
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address DynaBus ID
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (0), SnReady drops immediately
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 0005 ) -- Start Read cycle (4), SnReady should raise back since data is available
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 0005 ) -- Sample Read data (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 0005 ) -- Sample Read data (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 0005 ) -- Sample Read data (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000001A 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Finish Read command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove IOCS & address
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Regular PBus access for read through large map
Setup large map entry #3, write 16 addr MSB in MSB half of entry...
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000008E 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address large map #3 and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to large map #3
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000008E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Read memory word at addr 003ABCDE
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address memory & setup MemCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Read command, becomes not ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 98 1236AF37 ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhA, drive PBus
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 98 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA (invisible due to oracle skew)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 98 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhB, do not drive PBus
( 0 0000000000000000 0 1 ) ( 0 0 12345678 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, drive results
( 0 0000000000000000 0 1 ) ( 0 0 12345678 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- PBus access complete, PBus done
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 7856 ) -- Now ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 E 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 7856 ) -- Keep command one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 003ABCDE 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove read command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Read explicitely the PBus output register, should result in opposite byte order
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address PBus result register, most-significant bits (same as previously read...)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (0), SnReady drops immediately
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 5678 ) -- Start Read cycle (4), SnReady should raise back since data is available
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 5678 ) -- Sample Read data
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 5678 ) -- Sample Read data again
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000008 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Finish Read command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove IOCS & address
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Regular PBus access write through small map with one reject cycle
Setup small map entry #B, write 16 addr MSB in MSB half of entry...
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006E 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address large map #3 and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to large map #3
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006E 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Setup small map entry #B, write 16 addr LSB in LSB half of entry...
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006C 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address large map #3 and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to large map #3
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000006C 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write memory byte at logical addr 0000B123
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 0000B123 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address memory & setup MemCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 89 12345448 ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhA, drive PBus
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 89 XXXXXX24 ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA, invisible due to oracle skew
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 89 XXXXXX24 ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhB, keep driving PBus
( 0 0000000000000000 0 1 ) ( 0 1 XXXXXXXX ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 00 XXXXXX24 ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, drive results, slave issues a Reject
( 0 0000000000000000 0 1 ) ( 0 1 XXXXXXXX ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Thinking after PhB
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Reissue PhA
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA, invisible due to oracle skew
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Reissue PhB
( 0 0000000000000000 0 1 ) ( 0 0 XXXXXXXX ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, drive results, slave accepts command
( 0 0000000000000000 0 1 ) ( 0 1 XXXXXXXX ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- PBus access complete, PBus done
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Now ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 D 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep command one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 1 F 0000B123 0 2468 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove write command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Do a programmed access: write 13579BDF @ 12345678, then same programmed read with a fault
Write PBus addr register (low 2 bytes)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000004 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address PBus addr register and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus addr register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus addr register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000004 0 5678 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write PBus addr register (high 2 bytes)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000006 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address PBus addr register and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus addr register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus addr register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000006 0 1234 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write PBus data register (low 2 bytes)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address PBus data register and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus data register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000000 0 9BDF ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write PBus data register (high 2 bytes)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000002 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address PBus addr register and setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data for write to PBus addr register
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Write command, should become ready again (4)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep write pulse on one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000002 0 1357 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Terminate write cycle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write command register with PCmd=E1, a write command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup PCmdReg addr
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 E1 12345678 ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhA, drive PBus
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 E1 13579BDF ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA, invisible due to oracle skew
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 E1 13579BDF ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhB, keep driving PBus
( 0 0000000000000000 0 1 ) ( 0 0 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 1 00 13579BDF ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, drive results
( 0 0000000000000000 0 1 ) ( 0 1 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- PBus access complete, PBus done
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Now ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep command one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 00E1 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove write command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Write command register with PCmd=98, a read command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup PCmdReg addr
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup data
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Write command, becomes not ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Idle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 98 12345678 ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhA, drive PBus
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 98 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA, invisible due to oracle skew
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 98 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Begin PhB, stop driving PBus
( 0 0000000000000000 0 1 ) ( 1 1 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, issue reject & fault
( 0 0000000000000000 0 1 ) ( 1 1 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Thinking after PhB, Fault sensed
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 1 0 1 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Reissue PhA
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Second cycle of PhA, invisible due to oracle skew
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Reissue PhB
( 0 0000000000000000 0 1 ) ( 0 0 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 1 0 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- 2nd phase of PhB, drive results, slave accepts command
( 0 0000000000000000 0 1 ) ( 0 1 XXXXXXXX ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X 00 XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- PBus access complete, PBus done
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Now ready
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 D 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Keep command one last time
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 0000000C 0 0098 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove write command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Drop data & addresses
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
Read MSB of PBus error address register to check fault logged
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Address DynaBus ID
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Setup IOCS
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (0), SnReady drops immediately
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 0 F XXXXXX X XXXX ) -- Start Read cycle (3)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 1234 ) -- Start Read cycle (4), SnReady should raise back since data is available
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 1234 ) -- Sample Read data (0)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 1234 ) -- Sample Read data (1)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 E 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X 1234 ) -- Sample Read data (2)
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 2 F 00000016 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Finish Read command
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Remove IOCS & address
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
End of simulation
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
( 0 0000000000000000 0 1 ) ( 0 0 00000000 ) ( 0 1 0 3 F 00000000 0 0000 ) | ( 0 XXXXXXXXXXXXXXXX 0 ) ( 0 0 X XX XXXXXXXX ) ( 0 1 F XXXXXX X XXXX ) -- Idle
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