DefinePins: PROC [Args] RETURNS [Results] ~ {
Pins are described in LeftToRight, BottomToTop order as required by SC.
Internal: PROC [internal: Rope.ROPE] ~ {
Register wire on current side of SC block.
TBD
};
Pad: PROC [pad: Rope.ROPE] ~ {
Register wire on current side of chip.
TBD
};
External: PROC [internal: Rope.ROPE, pad: Rope.ROPE] ~ {
Wire is named internal on the SC block and pad on the chip boundary. The wire is an atomic input or output..
Pad[pad];
Internal[internal];
};
BusInternal: PROC [internal: Rope.ROPE, from: NAT, for: NAT] ~ {
Wire is named internal on the SC block, but does not propagate to the side of the chip. The wire is a bus, of which bits [from..from+for) are used, as for extractors. Each of its atomic wires are input or output. The MSB has the lowest position.
FOR i: NAT IN [from..from+for) DO
suffix: ROPE = IO.PutFR["[%g]", IO.int[i]];
Internal[internal.Concat[suffix]];
ENDLOOP;
};
BusExternal: PROC [internal: Rope.ROPE, pad: Rope.ROPE, from: NAT, for: NAT] ~ {
Wire is named internal on the SC block and pad on the chip boundary. The wire is a bus, of which bits [from..from+for) are used, as for extractors. Each of its atomic wires are input or output. The MSB has the lowest position.
FOR i: NAT IN [from..from+for) DO
suffix: ROPE = IO.PutFR["[%g]", IO.int[i]];
External[internal.Concat[suffix], pad.Concat[suffix]];
ENDLOOP;
};
IOInternal: PROC [input, output: Rope.ROPE] ~ {
Wire has an input and an output wires on the SC block, but does not propagate to the side of the chip. The input has the lowest coordinate on the SC block.
Internal[input];
Internal[output];
ENDLOOP;
};
IOExternal: PROC [input, output: Rope.ROPE, pad: Rope.ROPE] ~ {
Wire has an input and an output wires on the SC block and pad on the chip boundary. The input has the lowest coordinate on the SC block.
Pad[pad];
Internal[input];
Internal[output];
ENDLOOP;
};
IOBusInternal: PROC [input, output: Rope.ROPE, from: NAT, for: NAT] ~ {
Wire is an IO bus that does not propagate to the chip boundary. Components are extracted according to from and for. Order is in[0], out[0], in[1], out[1], ...
FOR i: NAT IN [from..from+for) DO
suffix: ROPE = IO.PutFR["[%g]", IO.int[i]];
IOInternal[input.Concat[suffix], output.Concat[suffix]];
ENDLOOP;
};
IOBusExternal: PROC [input, output: Rope.ROPE, pad: Rope.ROPE, from: NAT, for: NAT] ~ {
Wire is an IO bus that propagates to the chip boundary. Components are extracted according to from and for. Order is in[0], out[0], in[1], out[1], ...
FOR i: NAT IN [from..from+for) DO
suffix: ROPE = IO.PutFR["[%g]", IO.int[i]];
IOExternal[input.Concat[suffix], output.Concat[suffix], pad.Concat[suffix]];
ENDLOOP;
};
LeftSide: PROC ~ {
Define pins on left side
External["nHeaderIn", ""];
External["nGrant", ""];
External["ITIOBus", ""];
External["INT", ""];
External["MBReq", ""];
External["MBAck", ""];
External["PCLK", ""];
BusExternal["iDBus", "", 0, 7];
External["iDSelect", ""];
BusInternal["ExtraMapIn", 0, 6];
Internal["WExtra"];
BusInternal["LargeMapIn", 0, 14];
Internal["WLarge"];
BusInternal["SmallMapIn", 0, 22];
Internal["WSmall"];
BusInternal["MapOut", 0, 22];
BusInternal["MapAddr", 0, 4];
IOBusExternal["PBusIn", "PBusOut","" , 0, 32];
Internal["DrvPBus"];
BusInternal["FifoWAddr", 0, 4];
Internal["FifoWPulse"];
IOBusInternal["RqstIn", "RqstOut", 0, 81];
BusInternal["FifoRAddr", 0, 4];
External["iPReject", ""];
External["iPFault", ""];
BusExternal["iPCmd", "", 0, 7];
External["iPhA", ""];
External["iPhB", ""];
External["nRequest[0]", ""];
External["nSStopOut", ""];
External["nParityOut", ""];
};
RightSide: PROC ~ {
Define pins on left side
External["nParityIn", ""];
External["nSStopIn", ""];
External["nGLength", ""];
IOExternal["IOBAddrIn[31]", "nDEN", ""];
IOExternal["IOBAddrIn[30]", "DTnR", ""];
IOExternal["IOBAddrIn[29]", "MnINTA", ""];
BusExternal["IOBAddrIn", "", 24, 5];
IOBusExternal["IOBAddrIn", "IOBAddrOut", "", 0, 24];
IOExternal["nBHEIn", "nBHEOut", ""];
Internal["EnMOut"];
Internal["EnSOut"];
Internal["EnDOut"];
IOBusExternal["IOBDataIn", "IOBDataOut", "", 0, 16];
External["SnIOCS", ""];
External["SnMemCS", ""];
IOExternal["IOCheck", "nITFault", ""];
IOExternal["SnRD", "MnRD", ""];
IOExternal["SnWR", "MnWR", ""];
IOExternal["SnRDXnIOR", "MnIOR", ""];
IOExternal["SnWRXnIOW", "MnIOW", ""];
External["HReset", ""];
IOExternal["MnReady", "SnReady", ""];
External["nRequest[1]", ""];
External["nHeaderOut", ""];
External["CK", ""];
};
TopSide: PROC ~ {
Define pins on top side
IOBusExternal["nDataIn", "nDataOut", "", 0, 32];
};
BottomSide: PROC ~ {
Define pins on bottom side
IOBusExternal["nDataIn", "nDataOut", "", 32, 64];
};
};