DIRECTORY
Atom, Basics, BitOps, Dyn, DynaBusInterface, MCUtils, Ports, Rope, Simul2Sender;

Simul2SenderImpl: CEDAR PROGRAM
IMPORTS Atom, Basics, DynaBusInterface, MCUtils, Ports, Rope
EXPORTS Simul2Sender
~ BEGIN

DynaBusEvent: SIGNAL [msg: Rope.ROPE]= CODE;
Requestype: TYPE = {Nop,Hold,Lowp,Highp};
LengthCom: TYPE = {Short,Long};
ReplyBit: TYPE = DynaBusInterface.ReplyCmdField;
Quad: TYPE = DynaBusInterface.Quad;
Cmd: TYPE = DynaBusInterface.Cmd;
ModeError: TYPE = DynaBusInterface.ModeError;
Shared: TYPE = DynaBusInterface.Shared;
DeviceID: TYPE = DynaBusInterface.DeviceID;
Address: TYPE = DynaBusInterface.Address;
qZero: Quad = BitOps.BitQWordZero;
WordAsBits: TYPE = PACKED ARRAY [0..16) OF BOOL;
DWAsBits: TYPE = PACKED ARRAY [0..32) OF BOOL;
SimpleProc: TYPE = PROC[dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [];


bitSend: NAT=5;
bitStop: NAT=6;
bitShared: NAT=7;
bitOwner: NAT=8;
ClrMsgHere: NAT=9;


MsgSent: NAT = 0;  -- this bit is set when a message has been sent
MsgHere: NAT = 1;  -- this bit is set when a message is received

AllMsg: NAT = 13;
AnyId: NAT= 14;



StopSimul: SimpleProc ~ {
SIGNAL DynaBusEvent["End of Simulation"];
NextLine[dynaport];
};

NextLine: SimpleProc ~ {
dynaport.testProcList _ dynaport.testProcList.rest;
dynaport.countcycle _ 0;
};

Jump: SimpleProc ~ {
label: ATOM _ NARROW[params.first];
dynaport.testProcList _ NARROW[Atom.GetProp[$Simul2Sender, $PKList]];
WHILE dynaport.testProcList.first # label DO
NextLine[dynaport];
ENDLOOP;
};

B: PROC [b: BOOL] RETURNS [rb: REF ANY] = {rb _ NEW[BOOL _ b]};

WaitSync: SimpleProc ~ {
Flag: ATOM _ NARROW[params.first];
Cond: BOOL ;
IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond _ FALSE
ELSE Cond _ NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^;
IF Cond THEN  NextLine[dynaport];
};

SkipIfTrue: SimpleProc ~ {
Flag: ATOM _ NARROW[params.first];
Cond: BOOL;
IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond _ FALSE
ELSE Cond _ NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^;
NextLine[dynaport];
IF Cond THEN NextLine[dynaport];
};


SetFlag: SimpleProc ~ {
Flag: ATOM _ NARROW[params.first];
Atom.PutProp[$Sync,Flag, B[TRUE]];
NextLine[dynaport];
};

ClearFlag: SimpleProc ~ {
Flag: ATOM _ NARROW[params.first];
Atom.PutProp[$Sync,Flag, B[FALSE]];
NextLine[dynaport];
};

Wait: SimpleProc ~ {
countcycle: CARD _ NARROW[params.first, REF CARD]^;
IF dynaport.countcycle < countcycle THEN dynaport.countcycle _ dynaport.countcycle + 1
ELSE  NextLine[dynaport];
};

WaitMsgSent: SimpleProc ~ {
IF dynaport.status[MsgSent] = H THEN NextLine[dynaport];

};

WaitMsgReceived: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle =1  
THEN {
dynaport.countcycle _ 2}
ELSE IF dynaport.countcycle=2 
THEN {
dynaport.load _ H;
dynaport.rqlar[ClrMsgHere] _ L;
dynaport.countcycle _ 3 }
ELSE IF dynaport.countcycle=3 THEN {
dynaport.load _ L;
NextLine[dynaport] };
};

Init: SimpleProc ~ {
Ports.LCToLS[0,dynaport.rqlar];
Ports.LCToLS[0,dynaport.sendpar];
dynaport.send _ H; -- for this version send is not useful (only for DbugBus)
Ports.LCToLS[0,dynaport.alpha];
Ports.LCToLS[11111111H,dynaport.beta];
Ports.LCToLS[22222222H,dynaport.gama];
Ports.LCToLS[33333333H,dynaport.delta];
Ports.LCToLS[44444444H,dynaport.epsilon];
IF dynaport.countcycle<4 THEN
{ dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load _ H }
ELSE
{ dynaport.countcycle _ 0;
dynaport.load _ L };
NextLine[dynaport];
};

ReceiveAll:SimpleProc~ {
dynaport.sendpar[AllMsg] _ H;
dynaport.sendpar[AnyId] _ H;
IF dynaport.countcycle<4 THEN
{ dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load _ H }
ELSE
{ dynaport.countcycle _ 0;
dynaport.load _ L };
NextLine[dynaport];
};

StartStop: SimpleProc ~ {
SELECT dynaport.countcycle FROM
<5 => {
dynaport.rqlar[bitStop] _ L;
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load_ H }; 
IN [5..36] => {
dynaport.rqlar[bitStop] _ H;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load_ H};
IN [37..40] => {
dynaport.rqlar[bitStop] _ L;
dynaport.rqlar[ClrMsgHere] _ L;
dynaport.countcycle _ dynaport.countcycle+1};
ENDCASE => {
dynaport.load _ L;
NextLine[dynaport] };
};


convbits: PROC [data: CARDINAL] RETURNS [dataasbits: WordAsBits] ~ {
dataasbits _ LOOPHOLE[data]
};

cvcardbits: PROC [data: CARD] RETURNS [dataasbits: DWAsBits] ~ {
dataasbits _ LOOPHOLE[Basics.SwapHalves[LOOPHOLE[data]]]
};



MakeHeader: PROC [dynaport: Dyn.DynaPortState, cmd: Cmd, mode: ModeError _ TRUE, sh: Shared _ FALSE, id: DeviceID _ 0, add: Address _ qZero] RETURNS [] ~ {
header: Quad;
header _ qZero;
header _ DynaBusInterface.InsertCmd[header, cmd];
header _ DynaBusInterface.InsertModeError[header, mode];
header _ DynaBusInterface.InsertShared[header, sh];
header _ DynaBusInterface.InsertDeviceID[header, id];
header _ DynaBusInterface.InsertAddress[header, add];

dynaport.alpha[0] _  H; -- For the Header
dynaport.alpha[1] _  L; -- For the Parity
dynaport.alpha[2] _  L; -- For Spare
dynaport.alpha[3] _  L; -- For Spare
FOR bit: NAT IN [4..20) DO
dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[0]][bit-4]];
ENDLOOP;
FOR bit: NAT IN [20..36) DO
dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[1]][bit-20]];
ENDLOOP;
FOR bit: NAT IN [36..52) DO
dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[2]][bit-36]];
ENDLOOP;
FOR bit: NAT IN [52..68) DO
dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[3]][bit-52]];
ENDLOOP;
};


MakeData1: PROC [dynaport: Dyn.DynaPortState, d0: Quad] RETURNS [] ~ {
FOR bit: NAT IN [0..4) DO
dynaport.beta[bit]  _  L; 
dynaport.gama[bit]  _  L; 
dynaport.delta[bit]  _  L; 
dynaport.epsilon[bit] _  L; 
ENDLOOP;
FOR bit: NAT IN [4..20) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[0]][bit-4]];
dynaport.gama[bit] _ L;
dynaport.delta[bit] _ L;
dynaport.epsilon[bit] _ L;
ENDLOOP;
FOR bit: NAT IN [20..36) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[1]][bit-20]];
dynaport.gama[bit] _ L;
dynaport.delta[bit] _ L;
dynaport.epsilon[bit] _ L;
ENDLOOP;
FOR bit: NAT IN [36..52) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[2]][bit-36]];
dynaport.gama[bit] _ L;
dynaport.delta[bit] _ L;
dynaport.epsilon[bit] _ L;
ENDLOOP;
FOR bit: NAT IN [52..68) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[3]][bit-52]];
dynaport.gama[bit] _ L;
dynaport.delta[bit] _ L;
dynaport.epsilon[bit] _ L;
ENDLOOP;
};

MakeData4: PROC [dynaport: Dyn.DynaPortState, d0,d1,d2,d3: Quad] RETURNS [] ~ {
FOR bit: NAT IN [0..4) DO
dynaport.beta[bit]  _  L; 
dynaport.gama[bit]  _  L; 
dynaport.delta[bit]  _  L; 
dynaport.epsilon[bit] _  L; 
ENDLOOP;
FOR bit: NAT IN [4..20) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[0]][bit-4]];
dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[0]][bit-4]];
dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[0]][bit-4]];
dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[0]][bit-4]];
ENDLOOP;
FOR bit: NAT IN [20..36) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[1]][bit-20]];
dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[1]][bit-20]];
dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[1]][bit-20]];
dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[1]][bit-20]];
ENDLOOP;
FOR bit: NAT IN [36..52) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[2]][bit-36]];
dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[2]][bit-36]];
dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[2]][bit-36]];
dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[2]][bit-36]];
ENDLOOP;
FOR bit: NAT IN [52..68) DO
dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[3]][bit-52]];
dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[3]][bit-52]];
dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[3]][bit-52]];
dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[3]][bit-52]];
ENDLOOP;
};


SetRQL: PROC [dynaport: Dyn.DynaPortState, rq: Requestype, lg: LengthCom] RETURNS [] ~ {
SELECT rq FROM
Nop => {dynaport.rqlar[0] _ L; dynaport.rqlar[1] _ L};
Hold => {dynaport.rqlar[0] _ L; dynaport.rqlar[1] _ H};
Lowp => {dynaport.rqlar[0] _ H; dynaport.rqlar[1] _ L};
Highp => {dynaport.rqlar[0] _ H; dynaport.rqlar[1] _ H};
ENDCASE => ERROR;
dynaport.rqlar[2] _ IF lg=Short THEN L ELSE H;
};

CheckRcvCom: PROC [dynaport: Dyn.DynaPortState, cmd: Cmd] RETURNS [r: BOOL] ~ {
val:CARD _ 0;
val _ val + (IF dynaport.ialpha[8]=L THEN 0 ELSE 1);
val _ val + (IF dynaport.ialpha[7]=L THEN 0 ELSE 2);
val _ val + (IF dynaport.ialpha[6]=L THEN 0 ELSE 4);
val _ val + (IF dynaport.ialpha[5]=L THEN 0 ELSE 8);
val _ val + (IF dynaport.ialpha[4]=L THEN 0 ELSE 16);
r _  val=ORD[cmd]
};

CheckRcvData0: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ {
d0: Quad;
par1: LIST OF REF ANY _ params;
d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
r _ TRUE;

FOR bit: NAT IN [36..52) DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [52..68) DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE;
ENDLOOP;
};



CheckRcvData1: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ {
d0,d1: Quad;
par1: LIST OF REF ANY _ params;
d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
d1 _ NARROW[par1.first, REF Quad]^;
r _ TRUE;
FOR bit: NAT IN [4..20) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [20..36) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [36..52) DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE;
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [52..68) DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE;
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r _ FALSE;
ENDLOOP;
};



CheckRcvData4: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ {
d0, d1, d2, d3: Quad;
par1: LIST OF REF ANY _ params;
d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
d1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
d2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
d3 _ NARROW[par1.first, REF Quad]^;
r _ TRUE;
FOR bit: NAT IN [4..20) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[0]][bit-4]] THEN r _ FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r _ FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[0]][bit-4]] THEN r _ FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[0]][bit-4]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [20..36) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[1]][bit-20]] THEN r _ FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r _ FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[1]][bit-20]] THEN r _ FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[1]][bit-20]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [36..52) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r _ FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[2]][bit-36]] THEN r _ FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[2]][bit-36]] THEN r _ FALSE;
ENDLOOP;
FOR bit: NAT IN [52..68) DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r _ FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[3]][bit-52]] THEN r _ FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[3]][bit-52]] THEN r _ FALSE;
ENDLOOP;
};

SendRequest: SimpleProc~ {

SELECT dynaport.countcycle FROM
0 => { dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[bitSend] _ H; --bit send
dynaport.load _ H; };
1 => { dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[bitSend] _ H };
2 => { dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[bitSend] _ L };
ENDCASE => {dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load _ L;
NextLine[dynaport] };

};


WriteBlockRqst : SimpleProc~ {
data0, data1, data2, data3: Quad;
address: Quad _ NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY _ params.rest;
data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data3 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Highp, Long];

MakeHeader[dynaport: dynaport,cmd: WBRqst, add: address, mode: TRUE]; 
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};

FlushBlockRqst : SimpleProc~ {
data0, data1, data2, data3: Quad;
address: Quad _ NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY _ params.rest;
data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data3 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Highp, Long];

MakeHeader[dynaport: dynaport,cmd: FBRqst, add: address, mode: TRUE]; 
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};


ReadBlockRqst: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: RBRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0] ];
SendRequest[dynaport]

};

ReadBlockRply : SimpleProc~ {
data0, data1, data2, data3: Quad;
address: Quad _ NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY _ params.rest;
data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest;
data3 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Highp, Long];

MakeHeader[dynaport: dynaport,cmd: RBRply, add: address, mode: TRUE]; 
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};

WriteSingleRqst: SimpleProc ~ {
data0, address : Quad;
par1: LIST OF REF ANY _ params.rest;
address _ NARROW[params.first, REF Quad]^;
data0 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: WSRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]

};

CondWSRqst: SimpleProc ~ {
data0, address : Quad;
par1: LIST OF REF ANY _ params.rest;
address _ NARROW[params.first, REF Quad]^;
data0 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: CWSRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]

};


CondWSRply: SimpleProc ~ {
data0, address : Quad;
id: DeviceID;
data0 _ NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..68) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;

MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0];
SendRequest[dynaport]

};

CondWSRply1: SimpleProc ~ {
data0, address : Quad;
address _ NARROW[params.first, REF Quad]^;
data0 _ NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];


MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0];
SendRequest[dynaport]
};

DeMapRqst: SimpleProc ~ {
data0, address : Quad;
par1: LIST OF REF ANY _ params.rest;
address _ NARROW[params.first, REF Quad]^;
data0 _ NARROW[par1.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: DeMapRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]
};

DeMapRply: SimpleProc ~ {
address : Quad;
id: DeviceID;
data: Quad _ NARROW[params.first, REF Quad]^;


SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.
address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..68) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;


MakeHeader[dynaport: dynaport,cmd: DeMapRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};

DeMapRply1: SimpleProc ~ {
data0, address : Quad;
par1: LIST OF REF ANY _ params.rest;
address _ NARROW[params.first, REF Quad]^;
data0 _ NARROW[par1.first, REF Quad]^;


SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.


MakeHeader[dynaport: dynaport,cmd: DeMapRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data0];
SendRequest[dynaport]
};


WriteSingleRply: SimpleProc ~ {
address : Quad;
id: DeviceID;
data: Quad _ NARROW[params.first, REF Quad]^;


SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.
address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..68) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;


MakeHeader[dynaport: dynaport,cmd: WSRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};

WriteSingleRply1: SimpleProc ~ {
address,data : Quad;
address _ NARROW[params.first, REF Quad]^;
data _ NARROW[params.rest.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.

MakeHeader[dynaport: dynaport,cmd: WSRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};



MapRqst: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;
aid: Quad _ NARROW[params.rest.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport, cmd: MapRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: aid];
SendRequest[dynaport];
};

MapReply: SimpleProc ~ {
address: Quad;
flags: CARD;
id: DeviceID;

flags _ NARROW[params.first, REF CARD]^;
SetRQL[dynaport, Lowp, Short];

address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..64) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[64..68) DO 
address[3] _  address[3]*2 + (IF (cvcardbits[flags][bit-64+28]) THEN  1 ELSE 0); 	--Flags
ENDLOOP;


MakeHeader[dynaport: dynaport,cmd: MapRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0]];
SendRequest[dynaport]
};




IOWriteRqst: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;
data: Quad _ NARROW[params.rest.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};

IOWriteRply: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;
data: Quad _ NARROW[params.rest.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.

MakeHeader[dynaport: dynaport,cmd: IOWRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};


IOWriteRply0: SimpleProc ~ {
address: Quad;
id: DeviceID;


SetRQL[dynaport, Lowp, Short];	-- has to be low priority in order to be short.
address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..68) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;


MakeHeader[dynaport: dynaport,cmd: IOWRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: [0,0,0,0]];
SendRequest[dynaport]
};



IOReadRqst: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: IORRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0] ];
SendRequest[dynaport]
};

IOReadRply: SimpleProc ~ {
address: Quad _ NARROW[params.first, REF Quad]^;
data: Quad _ NARROW[params.rest.first, REF Quad]^;

SetRQL[dynaport, Lowp, Short];

MakeHeader[dynaport: dynaport,cmd: IORRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: data ];
SendRequest[dynaport]
};


IOReadRply0: SimpleProc ~ {
data: Quad _ NARROW[params.first, REF Quad]^;
address: Quad;
id: DeviceID;
SetRQL[dynaport, Lowp, Short];

address[0] _ 0;
address[1] _ 0;
address[2] _ 0;
address[3] _ 0;
id _ 0;
FOR bit: NAT  IN[11..21) DO
id _  id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[36..52) DO
address[2] _  address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;
FOR bit: NAT  IN[52..68) DO
address[3] _  address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); 
ENDLOOP;



MakeHeader[dynaport: dynaport,cmd: IORRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: data ];
SendRequest[dynaport]
};


WaitReply: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message  
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF dynaport.ialpha[8]=H THEN NextLine[dynaport]
ELSE dynaport.countcycle _ 0;
}
}
};


WaitMapRqst: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, MapRqst] 
THEN  NextLine[dynaport]
ELSE dynaport.countcycle _ 0; --wait a new message
}
}
};


WaitReadBlockRplyandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, RBRply] 
THEN {
IF  ~CheckRcvData4[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data4"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
}
}
};

WaitIOReadRplyandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, IORRply] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};


WaitIOWRplyandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, IOWRply] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitIOWRqstandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, IOWRqst] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitIOReadRqstandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, IORRqst] 
THEN {
IF  ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitReadBlockRqstandCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, RBRqst] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitReadBlockRqstandCheck1: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, RBRqst] 
THEN {
IF  ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};



WaitWriteSingleRqstAndCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, WSRqst] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitCondWriteSingleRqstAndCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, CWSRqst] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};

WaitCondWriteSingleRplyAndCheck: SimpleProc ~ {
IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0
THEN {
dynaport.countcycle _ 1;
dynaport.rqlar[ClrMsgHere] _ H;
dynaport.load _ H } 
ELSE
IF dynaport.countcycle=1  THEN dynaport.countcycle _2
ELSE {
IF  (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message 
THEN{
dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] _ L
}
ELSE IF dynaport.countcycle=6 THEN{
dynaport.load _ L;
IF CheckRcvCom[dynaport, CWSRply] 
THEN {
IF  ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle _ 0; --wait a new message
};
}
};


IOWrite0 : SimpleProc~ {
data, data0, data3, data4, data5, data6, data7, data8: CARD;
data1, data2: BOOL;
address: Quad _ [0,0,30H,0400H];
par1: LIST OF REF ANY _ params;
data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF BOOL]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF BOOL]^; par1 _ par1.rest;
data3 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data4 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data5 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data6 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data7 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data8 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;

SetRQL[dynaport, Lowp, Short];

data_ MCUtils.ComposeIOWrite0[ownerFifoDelay: data0, enbCorr: data1, enbOpReflect: data2, selRefCk: data3, gntDelay: data4, pchgDelay: data5, refDelay: data6, wrDelay: data7, rdDelay: data8];

MakeHeader[dynaport: dynaport, cmd: IOWRqst, add: address, mode: FALSE];	
MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data],Basics.LowHalf[data]] ];
SendRequest[dynaport]
};

IOWrite1 : SimpleProc~ {
data, data0, data1, data2, data3 : CARD;
address: Quad _ [0,0,30H,0401H];
par1: LIST OF REF ANY _ params;
data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data3 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;

SetRQL[dynaport, Lowp, Short];

data _ MCUtils.ComposeIOWrite1[banks: data0, ramAddWires: data1, bankAdd: data2, pageAdd: data3];

MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE]; 
MakeData1[dynaport: dynaport,d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]];
SendRequest[dynaport]
};

IOWrite2 : SimpleProc~ {
data, data0, data1, data2 : CARD;
address: Quad _ [0,0,30H,0402H];
par1: LIST OF REF ANY _ params;
data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data1 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest;
data2 _ NARROW[par1.first, REF CARD]^;

SetRQL[dynaport, Lowp, Short];

data_ MCUtils.ComposeIOWrite2[banks: data0, ramAddWires: data1, bankAdd: data2];

MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE]; 
MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]];
SendRequest[dynaport]
};

SendShOw : SimpleProc~ {
SO: Rope.ROPE _ NARROW[params.first, REF Rope.ROPE]^;
SELECT dynaport.countcycle FROM
0 => { dynaport.countcycle _ dynaport.countcycle+1;
SELECT TRUE FROM
Rope.Equal[SO, "S"] =>  dynaport.rqlar[bitShared] _ H; --bit Shared
Rope.Equal[SO, "O"] =>  dynaport.rqlar[bitOwner] _ H; --bit bitOwner
Rope.Equal[SO, "SO"] => {dynaport.rqlar[bitOwner] _ H; dynaport.rqlar[bitShared]_ H};
ENDCASE => ERROR;
dynaport.load _ H; };
1 => { dynaport.countcycle _ dynaport.countcycle+1;
dynaport.rqlar[bitShared] _ L;
dynaport.rqlar[bitOwner] _ L};
ENDCASE => {dynaport.countcycle _ dynaport.countcycle+1;
dynaport.load _ L;
NextLine[dynaport] };

};


C: PROC [c: CARD] RETURNS [rc: REF ANY] = {rc _ NEW[CARD _ c]};
Q: PROC [c: Quad] RETURNS [rc: REF ANY] = {rc _ NEW[Quad _ c]};
SendBus: PUBLIC PROC [dynaport: Dyn.DynaPortState] RETURNS [] ~ {
IF dynaport.testProcList = NIL THEN {
dynaport.testProcList _ NARROW[Atom.GetProp[$Simul2Sender, $PKList]];
};

DO

AtomDidSomething: PROC [atom: ATOM, params: LIST OF REF ANY] RETURNS [BOOL] =
{
v: REF ANY = Atom.GetProp[$Simul2Sender, atom];
IF v # NIL THEN {
spr: REF SimpleProc = NARROW[v];
spr^[dynaport, params];
RETURN[TRUE];
}
ELSE {
NextLine[dynaport];
RETURN[FALSE];
};
};

WITH dynaport.testProcList.first SELECT FROM
atom: ATOM => IF AtomDidSomething[atom, NIL] THEN EXIT;
list: LIST OF REF ANY => {
WITH list.first SELECT FROM
atom: ATOM => IF AtomDidSomething[atom, list.rest] THEN EXIT;
ENDCASE => ERROR;
};
ENDCASE => ERROR;
ENDLOOP;
};

Atom.PutProp[$Simul2Sender, $Init, NEW[SimpleProc _ Init]];
Atom.PutProp[$Simul2Sender, $ReceiveAll, NEW[SimpleProc _ ReceiveAll]];
Atom.PutProp[$Simul2Sender, $StartStop, NEW[SimpleProc _ StartStop]];
Atom.PutProp[$Simul2Sender, $Wait, NEW[SimpleProc _ Wait]];
Atom.PutProp[$Simul2Sender, $WaitMsgSent, NEW[SimpleProc _ WaitMsgSent]];
Atom.PutProp[$Simul2Sender, $WaitMsgReceived, NEW[SimpleProc _ WaitMsgReceived]];
Atom.PutProp[$Simul2Sender, $Jump, NEW[SimpleProc _ Jump]];
Atom.PutProp[$Simul2Sender, $WaitSync, NEW[SimpleProc _ WaitSync]];
Atom.PutProp[$Simul2Sender, $SetFlag, NEW[SimpleProc _ SetFlag]];
Atom.PutProp[$Simul2Sender, $ClearFlag, NEW[SimpleProc _ ClearFlag]];
Atom.PutProp[$Simul2Sender, $SkipIfTrue, NEW[SimpleProc _ SkipIfTrue]];
Atom.PutProp[$Simul2Sender, $StopSimul, NEW[SimpleProc _ StopSimul]];

Atom.PutProp[$Simul2Sender, $WriteBlockRqst, NEW[SimpleProc _ WriteBlockRqst]];
Atom.PutProp[$Simul2Sender, $ReadBlockRqst, NEW[SimpleProc _ ReadBlockRqst]];
Atom.PutProp[$Simul2Sender, $ReadBlockRply, NEW[SimpleProc _ ReadBlockRply]];
Atom.PutProp[$Simul2Sender, $WriteSingleRqst, NEW[SimpleProc _ WriteSingleRqst]];
Atom.PutProp[$Simul2Sender, $WriteSingleRply, NEW[SimpleProc _ WriteSingleRply]];
Atom.PutProp[$Simul2Sender, $WriteSingleRply1, NEW[SimpleProc _ WriteSingleRply1]];
Atom.PutProp[$Simul2Sender, $FlushBlockRqst, NEW[SimpleProc _ FlushBlockRqst]];
Atom.PutProp[$Simul2Sender, $CondWSRqst, NEW[SimpleProc _ CondWSRqst]];
Atom.PutProp[$Simul2Sender, $CondWSRply, NEW[SimpleProc _ CondWSRply]];
Atom.PutProp[$Simul2Sender, $CondWSRply1, NEW[SimpleProc _ CondWSRply1]];
Atom.PutProp[$Simul2Sender, $DeMapRqst, NEW[SimpleProc _ DeMapRqst]];
Atom.PutProp[$Simul2Sender, $DeMapRply, NEW[SimpleProc _ DeMapRply]];
Atom.PutProp[$Simul2Sender, $DeMapRply1, NEW[SimpleProc _ DeMapRply1]];

Atom.PutProp[$Simul2Sender, $WaitMapRqst, NEW[SimpleProc _ WaitMapRqst]];
Atom.PutProp[$Simul2Sender, $MapReply, NEW[SimpleProc _ MapReply]];

Atom.PutProp[$Simul2Sender, $IOReadRqst, NEW[SimpleProc _ IOReadRqst]];
Atom.PutProp[$Simul2Sender, $IOReadRply, NEW[SimpleProc _ IOReadRply]];
Atom.PutProp[$Simul2Sender, $IOReadRply0, NEW[SimpleProc _ IOReadRply0]];
Atom.PutProp[$Simul2Sender, $MapRqst, NEW[SimpleProc _ MapRqst]];
Atom.PutProp[$Simul2Sender, $IOWriteRqst, NEW[SimpleProc _ IOWriteRqst]];
Atom.PutProp[$Simul2Sender, $IOWriteRply, NEW[SimpleProc _ IOWriteRply]];
Atom.PutProp[$Simul2Sender, $IOWriteRply0, NEW[SimpleProc _ IOWriteRply0]];

Atom.PutProp[$Simul2Sender, $WaitReply, NEW[SimpleProc _ WaitReply]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRplyandCheck, NEW[SimpleProc _ WaitReadBlockRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOReadRplyandCheck, NEW[SimpleProc _ WaitIOReadRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOWRplyandCheck, NEW[SimpleProc _ WaitIOWRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOWRqstandCheck, NEW[SimpleProc _ WaitIOWRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOReadRqstandCheck, NEW[SimpleProc _ WaitIOReadRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck, NEW[SimpleProc _ WaitReadBlockRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck1, NEW[SimpleProc _ WaitReadBlockRqstandCheck1]];
Atom.PutProp[$Simul2Sender, $WaitWriteSingleRqstAndCheck, NEW[SimpleProc _ WaitWriteSingleRqstAndCheck]];
Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRqstAndCheck, NEW[SimpleProc _ WaitCondWriteSingleRqstAndCheck]];
Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRplyAndCheck, NEW[SimpleProc _ WaitCondWriteSingleRplyAndCheck]];





Atom.PutProp[$Simul2Sender, $IOWrite0, NEW[SimpleProc _ IOWrite0]];
Atom.PutProp[$Simul2Sender, $IOWrite1, NEW[SimpleProc _ IOWrite1]];
Atom.PutProp[$Simul2Sender, $IOWrite2, NEW[SimpleProc _ IOWrite2]];
Atom.PutProp[$Simul2Sender, $SendShOw, NEW[SimpleProc _ SendShOw]];



Atom.PutProp[$Simul2Sender, $PKList, LIST[
  $Init,
$Nop,
  LIST[$Jump, $Nop]
]];
END.

ΐSimul2SenderImpl.mesa
Copyright Σ 1987 by Xerox Corporation.  All rights reserved.
Created by Jean Gastinel, July 10, 1988 1:30:06 pm PDT
Hoel, April 29, 1988 5:21:37 pm PDT
Pradeep Sindhu May 5, 1988 7:39:04 pm PDT




Service Types

HARDWARE DEFINITIONS

Definition of the register rqlar
Definition of the Status register
Definition of the RecPar register
Service Procs

Jump to cycle line number : lnb
Interprocess Synchronisation

This proc is use for synchronisation. It tests the value of a parameter atom $Flag
This proc is used for synchronisation. It tests the value of the parameter atom $Flag.
If the parameter is True, the next instruction is skiped. If it is Not True the 
following instructions are normally executed.
This proc is use for synchronisation. It Set the value of a parameter atom $Flag
to TRUE
This proc is use for synchronisation. It Clears the value of a parameter atom $Flag
to FALSE
This proc count "countcycle" cycle before going to the next instruction
This proc tests the bit "MsgSent" of status, if it is H goto Nextline
This proc tests the  bit "MsgHere" of status, if it is H goto Nextline
After clear this bit in setting and resetting the bit "ClrMsgHere" of the rqlar register

This proc initialise the dynaport
This proc initialise the "sendpar" for receiving all the messages with any identifier
This proc builds a one 64-bits word of data

i=0 for the Header, i=1 for the Parity, i=2 & 3 for Spare
This proc builds four 64-bits words of data

i=0 for the Header, i=1 for the Parity, i=2 & 3 for Spare
This proc set the request bits and the length in the register SendPar 
This proc tests if the received command is cmd
This proc tests only that the address part of the received data equal the parameter 
This proc tests if the received Data on one word equals the parameter
This proc tests if the received Data on four words equals the parameter
With the bit "load" active, this proc set and reset the bit "send" 
DynaBus Commands




This proc send a WriteBlock Request command at the address "address", with value "data"
"address" is the first parameter, "data" is the second

This proc send a FlushBlockRqst  command at the address "address", with value "data"
"address" is the first parameter, "data" is the second

This proc send a ReadBlock Request command at the address "address"

This proc send a ReadBlockRply  command at the address "address", with value "data"
"address" is the first parameter, "data" is the second

This proc send a WriteSingleRqst  command at the address "address"

This proc send a CondWriteSingleRqst  command at the address "address"

This proc send a CondWriteSingleRply command with the parameters of the previous command, exept the data

This proc send a CondWriteSingleRply command with the given parameters 

This proc send a DeMapRqst  command at the address "address"

This proc send a DeMap Reply command with the previously received parameter

This proc send a DeMap Reply command with the previously received parameter

This proc send a Write Single Reply command with the previously received parameter

This proc send a Write Single Reply command with the given parameters

This proc send a Map Request command. The first parameter is the page address (Quad),
the second the aid (Quad)

This proc send a MapReply  command with the previous received parameter.
The parameter are the flags, which are put on the 4 low order bits of the address

This proc send a IOWrite Request command. The first parameter is the address,
the second the Data

This proc send a IOWrite Reply command. The first parameter is the address,
the second the Data

This proc send a IOWrite Reply command with the previously received parameter

This proc send a IORead Request command at the address "address"

This proc send a IOReadRply  command at the address "address"

This proc send a IOReadRply  with the previously received parameter (for the DevId & the address) and need on parameter more for the returned data

This proc tests the  bit "MsgHere" of status, if it is H  we clear this bit in setting 
and resetting the bit "ClrMsgHere". After we test if the msg was a reply :
 if yes goto Nextline, if not wait an another message

This proc tests the  bit "MsgHere" of status, if it is H  we clear this bit in setting 
and resetting the bit "ClrMsgHere". After we test if the msg was a MapRqst :
 if yes goto Nextline, if not wait an another message

This proc tests wait a ReadBlockReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a IOReadReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a IOWriteReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a IOWRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a IOReadRqst. First we test if the msg was the good command If not we wait an another message.

This proc tests wait a RBRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.

Same that WaitReadBlockRqstandCheck but without the testing of the second word.

This proc tests wait a WSRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a CondWSRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.

This proc tests wait a CondWSRply. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.

Special Memory Controller Commands


This proc send a IOWrite Request command in the register of address "00300400H", with value a
data computed by MCUtils.ComposeIOWrite0


This proc send a IOWrite Request command in the register of address  "00300401H", with 
a data value computed by MCUtils.ComposeIOWrite1


This proc send a IOWrite Request command in the register of address  "00300402H", with 
a data value computed by MCUtils.ComposeIOWrite2

This proc activates the Shared line, Owner line or both, depending of the
parameter which is a Rope which value is "S", "O" or "SO"



Simulation Procs
DynaBus Commands
Special Memory Controller Commands



Change Log

4-28-88:  Change IOAddress of IOWrite0, IOWrite1, and IOWrite2 to be consistent with having the Memory Controller have DynaBusId=1 (not 0).
4-29-88:  Added $IOWriteRply command.  JHH.


Κ/Ϊ˜
codeš
œ™Kš
œ<™<Kš
œ6™6K™#K™)—K™K™š
Οk	˜	Kš
œP˜P—K˜KšΠblœœ
˜Kšœ5˜<Kšœ
˜šœ˜K˜—K™K™Kš
Οb
™
K™Kšœœœœ
˜,Kšœœ˜)Kšœœ˜Kšœ
œ"˜0Kšœœ˜#Kšœœ˜!Kšœœ˜-Kšœœ˜'Kšœ
œ˜+Kšœ	œ˜)Kš
œ"˜"Kšœœœ
œ	œ
œ
˜0Kšœ
œœ
œ	œ
œ
˜.Kšœœœ&œ
œ
œ
œœœ˜`K˜K˜Kš
Ÿ™K™Kš
œ ™ Kšœ	œ˜Kšœ	œ˜Kšœœ˜Kšœ
œ˜Kšœœ˜K˜K˜K™!K˜BK˜@K˜K™!Kš
œ˜Kš
œ˜K˜K˜K˜Kš
Ÿ
™
K™šŸ	œ˜Kšœ#˜)Kš
œ˜K˜K˜—šΟnœ˜Kš
œ3˜3Kš
œ˜K˜—K˜š œ˜K™Kšœœœ˜#Kšœœ'˜Ešœ%˜,Kš
œ˜Kšœ
˜—K˜K˜—Kš 
œœœœœ
œ
œ
œ˜?K˜™K™—š œ˜Kš
œR™RKšœœœ˜"Kšœœ
˜Kšœœ
œœ
œœœ
œ˜iKšœœ˜!K˜K˜—šŸ
œ˜Kš
œΥ
™Υ
Kšœœœ˜"Kšœœ
˜Kšœœ
œœ
œœœ
œ˜iKš
œ˜Kšœœ˜ Kš
œ˜—K˜š œ˜Kš
œX™XKšœœœ˜"Kšœœ˜"Kš
œ˜K˜—š 	œ˜Kš
œ\™\Kšœœœ˜"Kšœœ˜#Kš
œ˜K˜K˜—š œ˜Kš
œG™GKš	œœœœ
œ˜3šœ"œ.˜VKšœ˜—K˜—K˜š œ˜K™Ešœ6˜8K˜—K˜—K˜š œ˜K™FKš
œX™XK™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜šœ˜šœ˜Kš
œ˜—šœ
œ˜šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—šœ
œœ˜$Kš
œ˜Kš
œ˜—————K˜K˜—š œ˜K™!Kš
œ˜Kš
œ!˜!KšœΟc9˜LKš
œ˜Kš
œ&˜&Kš
œ&˜&Kš
œ'˜'Kš
œ)˜)šœ˜Kš
œ.˜.Kš
œ˜Kš
˜Kš
œ˜Kš
œ˜—Kš
œ˜K˜K˜—š 
œ˜K™UKš
œ˜Kš
œ˜šœ˜Kš
œ.˜.Kš
œ˜Kš
˜Kš
œ˜Kš
œ˜—Kš
œ˜K˜K˜—šŸ	œ˜šœ˜š
œ˜Kš
œ˜Kš
œ,˜,Kš
œ˜—šœ
˜Kš
œ˜Kš
œ˜Kš
œ,˜,Kš
œ˜—šœ˜Kš
œ˜Kš
œ˜Kš
œ-˜-—šœ˜Kš
œ˜Kš
œ˜——K˜K˜—K˜šŸœœœœ˜DKšœ
œ˜K˜—K˜šŸ
œœœœ˜@Kšœ
œœ˜8K˜K˜K˜K˜—š
 
œœ;œœ*œ˜›
Kš
œ
˜
Kš
œ˜Kš
œ1˜1Kš
œ8˜8Kš
œ3˜3Kš
œ5˜5Kš
œ5˜5K˜Kšœ‘˜)Kšœ‘˜)Kšœ‘˜$Kšœ‘˜$šœ
œ	˜Kš
œ@˜@Kšœ
˜—šœ
œ
˜Kš
œA˜AKšœ
˜—šœ
œ
˜Kš
œA˜AKšœ
˜—šœ
œ
˜Kš
œA˜AKšœ
˜—K˜K˜—K˜š 	œœ)œ˜FK™+K™šœ
œ˜Kšœ‘œ‘œ‘™9Kš
œ˜Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—šœ
œ	˜Kš
œ;˜;Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—K˜K˜—š 	œœ2œ˜OK™+K™šœ
œ˜Kšœ‘œ‘œ‘™9Kš
œ˜Kš
œ˜Kš
œ˜Kš
œ˜Kšœ
˜—šœ
œ	˜Kš
œ;˜;Kš
œ;˜;Kš
œ<˜<Kš
œ>˜>Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ<˜<Kš
œ=˜=Kš
œ?˜?Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ<˜<Kš
œ=˜=Kš
œ?˜?Kšœ
˜—šœ
œ
˜Kš
œ<˜<Kš
œ<˜<Kš
œ=˜=Kš
œ?˜?Kšœ
˜—K˜K˜—K˜š œœ>œ˜XK™Fšœ˜Kš
œ6˜6Kš
œ7˜7Kš
œ7˜7Kš
œ8˜8Kšœœ
˜—Kšœœ
œœ˜.K˜K˜—šΠbnœœ)œœ˜OK™.Kšœœ˜
Kšœœœœ˜4Kšœœœœ˜4Kšœœœœ˜4Kšœœœœ˜4Kšœœœœ˜5Kšœ	œ˜K˜K˜—šŸ
œœ'œ
œ
œ
œœœœ˜gK™TKš
œ	˜	Kš	œœ
œ
œ
œ
˜Kšœœ
œ˜5Kšœ˜	K˜šœœ
œ
˜Kšœ@œ˜QKšœ
˜—šœœ
œ
˜Kšœ@œ˜QKšœ
˜—K˜K˜—˜K˜—šŸ
œœ'œ
œ
œ
œœœœ˜gK™EKš
œ˜Kš	œœ
œ
œ
œ
˜Kšœœ
œ˜5Kšœœ
œ˜#Kšœ˜	šœ
œ	˜Kšœ=œœ
˜OKšœ
˜—šœ
œ
˜Kšœ?œ˜PKšœ
˜—šœœ
œ
˜Kšœ@œ˜QKšœ?œ˜PKšœ
˜—šœœ
œ
˜Kšœ@œ˜QKšœ?œ˜PKšœ
˜—K˜K˜—K˜K˜šŸ
œœ'œ
œ
œ
œœœœ˜gK™GKš
œ˜Kš	œœ
œ
œ
œ
˜Kšœœ
œ˜5Kšœœ
œ˜5Kšœœ
œ˜5Kšœœ
œ˜#Kšœ˜	šœ
œ	˜Kšœ>œœ
˜OKšœ=œœ
˜OKšœ>œœ
˜PKšœAœœ
˜RKšœ
˜—šœ
œ
˜Kšœ?œ˜PKšœ?œ˜PKšœ@œ˜QKšœBœ˜SKšœ
˜—šœœ
œ
˜Kšœ?œ˜PKšœ?œ˜PKšœ@œ˜QKšœBœ˜SKšœ
˜—šœœ
œ
˜Kšœ?œ˜PKšœ?œ˜PKšœ@œ˜QKšœBœ˜SKšœ
˜—K˜K˜—Kš œ˜˜K™Cšœ˜Kš
œ3˜3Kšœ‘
˜'Kš
œ˜Kš
œ3˜3Kš
œ˜Kš
œ3˜3Kš
œ˜Kšœ1˜8Kš
œ˜Kš
œ˜—K˜K˜K˜K˜—Kš
ž™K™K™K™K™šŸœ˜Kš
œW™WK™6K™Kš
œ!˜!Kšœœœ˜0Kš	œœ
œ
œ
œ˜$Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜&K˜Kš
œ˜K˜Kšœ?œ˜FKš
œJ˜JKš
œ˜K˜K˜—šŸœ˜Kš
œT™TK™6K™Kš
œ!˜!Kšœœœ˜0Kš	œœ
œ
œ
œ˜$Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜&K˜Kš
œ˜K˜Kšœ?œ˜FKš
œJ˜JKš
œ˜K˜—˜K˜—šŸ
œ˜Kš
œC™CK™Kšœœœ˜0K˜Kš
œ˜K˜Kšœ?œ˜EKš
œ.˜.Kš
œ˜K˜K˜—šŸ
œ˜Kš
œS™SK™6K™Kš
œ!˜!Kšœœœ˜0Kš	œœ
œ
œ
œ˜$Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜8Kšœœ
œ˜&K˜Kš
œ˜K˜Kšœ?œ˜FKš
œJ˜JKš
œ˜K˜K˜—šŸœ˜Kš
œB™BK™Kš
œ˜Kš	œœ
œ
œ
œ˜$Kšœ
œœ˜*Kšœœ
œ	˜'Kš
œ˜K˜Kšœ?œ˜EKš
œ*˜*Kš
œ˜K˜K˜K˜—šŸ
œ˜Kš
œF™FK™Kš
œ˜Kš	œœ
œ
œ
œ˜$Kšœ
œœ˜*Kšœœ
œ	˜'Kš
œ˜K˜Kšœ@œ˜FKš
œ*˜*Kš
œ˜K˜K˜—K˜
šŸ
œ˜Kš
œh™hK™Kš
œ˜Kš
œ
˜
Kšœœœ˜(Kš
œ˜Kš
œ˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—K˜Kšœ@œ˜FKš
œJ˜JKš
œ˜K˜K˜K˜—šŸœ˜Kš
œG™GK™Kš
œ˜Kšœ
œœ˜*Kšœœœ˜-Kš
œ˜K˜K˜Kšœ@œ˜FKš
œJ˜JKš
œ˜K˜—šŸ	œ˜Kš
œ<™<K™Kš
œ˜Kš	œœ
œ
œ
œ˜$Kšœ
œœ˜*Kšœœ
œ	˜'Kš
œ˜K˜KšœBœ˜HKš
œ*˜*Kš
œ˜K˜K˜—šŸ	œ˜Kš
œK™KK™Kš
œ˜Kš
œ
˜
Kšœ
œœ˜-K˜K˜KšœΟe0˜NK˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—K˜K˜KšœJœ˜QKš
œ'˜'Kš
œ˜K˜—K˜šŸ
œ˜Kš
œK™KK™Kš
œ˜Kš	œœ
œ
œ
œ˜$Kšœ
œœ˜*Kšœœ
œ	˜'K˜Kšœ£0˜NK˜K˜KšœBœ˜IKš
œ(˜(Kš
œ˜K˜—K˜K˜šŸœ˜Kš
œR™RK™Kš
œ˜Kš
œ
˜
Kšœ
œœ˜-K˜K˜Kšœ£0˜NK˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—K˜K˜KšœGœ˜NKš
œ'˜'Kš
œ˜K˜—K˜šŸœ˜ Kš
œE™EK™Kš
œ˜Kšœ
œœ˜*Kšœœœ˜,K˜Kšœ£0˜NK˜Kšœ?œ˜FKš
œ'˜'Kš
œ˜K˜—K˜K˜K˜š’œ˜Kš
œo™oK™Kšœœœ˜0Kšœœœ˜1K˜Kš
œ˜K˜KšœAœ˜HKš
œ'˜'Kš
œ˜K˜K˜—š’œ˜Kš
œš
™š
K™Kš
œ˜Kšœœ
˜Kš
œ˜Kšœœœ
œ˜(Kš
œ˜K˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	œ
˜Kšœœ œœ‘˜YKšœ
˜—K˜K˜KšœHœ˜OKš
œ-˜-Kš
œ˜K˜—K˜
šŸœ˜Kš
œa™aK™Kšœœœ˜0Kšœ
œœ˜2K˜Kš
œ˜K˜Kšœ@œ˜GKš
œ'˜'Kš
œ˜K˜—šŸœ˜Kš
œ_™_K™Kšœœœ˜0Kšœ
œœ˜2K˜Kšœ£0˜NK˜Kšœ@œ˜GKš
œ'˜'Kš
œ˜K˜K˜
—šŸœ˜Kš
œM™MK™Kš
œ˜Kš
œ˜K˜Kšœ£0˜NK˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—K˜K˜KšœHœ˜OKš
œ,˜,Kš
œ˜K˜K˜
—K˜šŸ
œ˜Kš
œ@™@K™Kšœœœ˜0K˜Kš
œ˜K˜Kšœ@œ˜GKš
œ.˜.Kš
œ˜K˜K˜—šŸ
œ˜Kš
œ=™=K™Kšœœœ˜0Kšœ
œœ˜2K˜Kš
œ˜K˜Kšœ@œ˜GKš
œ)˜)Kš
œ˜K˜—šŸœ˜Kš
œ’
™’
K™Kšœ
œœ˜-Kš
œ˜Kš
œ
˜
Kš
œ˜K˜Kš
œ˜K˜K˜K˜Kš
œ˜šœœœ	˜Kšœœœœ˜8Kšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—šœœœ	˜Kšœœœœ˜HKšœ
˜—K˜K˜K˜KšœHœ˜OKš
œ)˜)Kš
œ˜K˜—K˜šŸ	œ˜K™WKš
œJ™JK™5K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜šœœ˜5Kšœ˜šœ8‘œ˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœœ˜/Kšœ˜—Kš
œ
˜
——K˜
———K˜—šŸœ˜K™WKš
œL™LK™5K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"Kšœ˜Kšœ‘˜2—Kš
œ
˜
——K˜
———Kš
œ˜—šŸœ˜)Kš
œσ
™σ
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ˜!šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ
˜
——K˜
———K˜—šŸœ˜&Kš
Ϲ
™π
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜#Kš
œρ
™ρ
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜#Kš
œγ
™γ
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜&Kš
œs™sK™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜)Kš
œβ
™β
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ˜!šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜*Kšœ
Ÿœ,™OK™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ˜!šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—K˜
šŸœ˜+Kš
œβ
™β
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ˜!šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—šŸœ˜/Kš
œζ
™ζ
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—K˜šŸœ˜/š
œζ
™ζ
K™šœœ˜:šœ˜Kš
œ˜Kš
œ˜Kš
œ˜—š
˜Kšœœ˜5šœ˜šœ9‘˜Wšœ
˜Kš
œ,˜,Kš
œ˜Kš
œ
˜
—šœ
œœ
˜#Kš
œ˜šœ ˜"šœ˜Kšœ#œ
œ-˜]Kš
œ˜—Kšœ‘˜2—Kš
œ˜——K˜
———K˜—K˜K˜—Kš
ž"™"K™K™šŸœ˜Kš
œ]™]Kš
œ(™(K™K™Kšœ7œ
˜<Kšœ˜Kš
œ ˜ Kš	œœ
œ
œ
œ
˜Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8K˜Kš
œ˜K˜Kš
œΏ
˜Ώ
K˜KšœAœ˜IKš
œU˜UKš
œ˜K˜K˜—šŸœ˜Kš
œW™WKš
œ0™0K™K™Kšœ#œ
˜(Kš
œ ˜ Kš	œœ
œ
œ
œ
˜Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8K˜Kš
œ˜K˜Kš
œa˜aK˜Kšœ@œ˜HKš
œT˜TKš
œ˜K˜K˜—šŸœ˜Kš
œW™WKš
œ0™0K™Kšœœ
˜!Kš
œ ˜ Kš	œœ
œ
œ
œ
˜Kšœœ
œ
œ˜8Kšœœ
œ
œ˜8Kšœœ
œ
œ˜&K˜Kš
œ˜K˜Kš
œP˜PK˜Kšœ@œ˜HKš
œU˜UKš
œ˜K˜K˜—šŸœ˜K™IKš
œ9™9K™Kš	œ	œœœœ˜5šœ˜š
œ3˜3šœ
œ
˜Kšœœ*‘˜CKšœœ)‘˜DKšœœH˜UKšœœ
˜—Kš
œ˜—š
œ3˜3Kš
œ˜Kš
œ˜—šœ1˜8Kš
œ˜Kš
œ˜——K˜K˜—K˜˜K™K™—Kš 
œœœœœ
œ
œ
œ˜?KšŸ
œœœœ
œ
œ˜?
head™šŸœœ
œœ˜Ašœœ
œ˜%Kšœœ'˜EKš
œ˜K˜—Kš
˜˜š œœœ
œ
œ
œ
œœœ˜MKš
œ
˜
Kšœœ
œ%˜/šœœ
œ˜Kšœœœ˜ Kš
œ˜Kšœ
œ˜
K˜
—šœ˜Kš
œ˜Kšœ
œ˜Kš
œ˜—Kš
œ˜K˜—šœœ
˜,Kšœœœœœ
œ
˜7š	œœ
œ
œ
œ˜šœœ
˜Kš	œœœ#œ
œ
˜=Kšœœ
˜—K˜—Kšœœ
˜—Kšœ
˜—K˜—K˜Kšœ#œ˜;Kšœ)œ˜GKšœ(œ˜EKšœ#œ˜;Kšœ*œ˜IKšœ.œ ˜QKšœ#œ˜;Kšœ'œ˜CKšœ&œ˜AKšœ(œ˜EKšœ)œ˜GKšœ(œ˜EK˜K™Kšœ-œ˜OKšœ,œ˜MKšœ,œ˜MKšœ.œ ˜QKšœ.œ ˜QKšœ/œ!˜SKšœ-œ˜OKšœ)œ˜GKšœ)œ˜GKšœ*œ˜IKšœ(œ˜EKšœ(œ˜EKšœ)œ˜GK˜Kšœ*œ˜IKšœ'œ˜CK˜Kšœ)œ˜GKšœ)œ˜GKšœ*œ˜IKšœ&œ˜AKšœ*œ˜IKšœ*œ˜IKšœ+œ˜KK˜Kšœ(œ˜EKšœ8œ*˜eKšœ5œ'˜_Kšœ2œ$˜YKšœ2œ$˜YKšœ5œ'˜_Kšœ8œ*˜eKšœ9œ+˜gKšœ:œ,˜iKšœ>œ0˜qKšœ>œ0˜qK˜K˜K˜K˜K˜Kš
œ"™"Kšœ'œ˜CKšœ'œ˜CKšœ'œ˜CKšœ'œ˜CK˜K˜K˜šœ%œ
˜*Kš
œ˜Kš
œ˜Kšœ
˜Kš
œ˜—K™—Kšœ
˜K™K™Kš
Ÿ
™
K™K™‹
K™+L™K™J˜—…—”<ΰΦ