<> <> <> <<>> <> <<>> DIRECTORY Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rope, Rosemary, RosemaryUser; VarRegImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary ~ BEGIN CellType : TYPE = Core.CellType; Wire: TYPE = Core.Wire; value: CARD _ 0; VarRegState: TYPE = REF VarRegStateRec; VarRegStateRec: TYPE = RECORD[ reg: Ports.LevelSequence, -- hold the value Q: CARD, -- the output Clock: CARD, b: CARD ]; <> VarRegDef: PUBLIC PROC [b: CARD] RETURNS [ct: CellType] ~ { <> public: Wire _ CoreCreate.WireList[ LIST[ CoreCreate.Seq["Q",8], "Clock" ]]; <> ct _ CoreClasses.CreateUnspecified[public: public]; CoreProperties.PutCellTypeProp[ct,$b,NEW[CARD _ b]]; [] _ Rosemary.BindCellType[cellType: ct, roseClassName: VarReg]; <> Ports.InitPorts[ct, ls, drive,"Q"]; Ports.InitPorts[ct, l, none,"Clock"]; }; <<>> VarRegInit: Rosemary.InitProc = { <> <<--PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY _ NIL] RETURNS [stateAny: REF ANY _ NIL]-->> vareg: VarRegState _ IF oldStateAny=NIL THEN NEW[VarRegStateRec] ELSE NARROW[oldStateAny, VarRegState]; vareg.reg _ NEW[Ports.LevelSequenceRec[8]]; Ports.SetLS[vareg.reg, X]; [vareg.Q] _ Ports.PortIndexes[cellType.public,"Q"]; [vareg.Clock] _ Ports.PortIndexes[cellType.public,"Clock"]; vareg.b _ NARROW[CoreProperties.GetCellTypeProp[cellType, $b], REF CARD]^; stateAny _ vareg; }; <<>> VarRegEval: Rosemary.EvalProc = { <<--PROC [p: Ports.Port, stateAny: REF ANY, clockEval: BOOL]-->> <<>> vareg: VarRegState _ NARROW[stateAny]; Ports.LCToLS[(value / vareg.b),vareg.reg]; <> Ports.CopyLS[from: vareg.reg, to: p[vareg.Q].ls]; }; VarReg: Core.ROPE = Rosemary.Register[roseClassName: "VarRegDef", init: VarRegInit, evalSimple: VarRegEval, scheduleIfClockEval: TRUE]; <<>> END.