<> <> <> <> <> <<>> <<>> DIRECTORY Atom, Basics, BitOps, Dyn, DynaBusInterface, MCUtils, Ports, Rope, Simul2Sender; Simul2SenderImpl: CEDAR PROGRAM IMPORTS Atom, Basics, DynaBusInterface, MCUtils, Ports, Rope EXPORTS Simul2Sender ~ BEGIN <<>> <<>> <> <<>> DynaBusEvent: SIGNAL [msg: Rope.ROPE]= CODE; Requestype: TYPE = {Nop,Hold,Lowp,Highp}; LengthCom: TYPE = {Short,Long}; ReplyBit: TYPE = DynaBusInterface.ReplyCmdField; Quad: TYPE = DynaBusInterface.Quad; Cmd: TYPE = DynaBusInterface.Cmd; ModeError: TYPE = DynaBusInterface.ModeError; Shared: TYPE = DynaBusInterface.Shared; DeviceID: TYPE = DynaBusInterface.DeviceID; Address: TYPE = DynaBusInterface.Address; qZero: Quad = BitOps.BitQWordZero; WordAsBits: TYPE = PACKED ARRAY [0..16) OF BOOL; DWAsBits: TYPE = PACKED ARRAY [0..32) OF BOOL; SimpleProc: TYPE = PROC[dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS []; <> <<>> <> bitSend: NAT=5; bitStop: NAT=6; bitShared: NAT=7; bitOwner: NAT=8; ClrMsgHere: NAT=9; <> MsgSent: NAT = 0; -- this bit is set when a message has been sent MsgHere: NAT = 1; -- this bit is set when a message is received <> AllMsg: NAT = 13; AnyId: NAT= 14; <> <<>> StopSimul: SimpleProc ~ { SIGNAL DynaBusEvent["End of Simulation"]; NextLine[dynaport]; }; NextLine: SimpleProc ~ { dynaport.testProcList _ dynaport.testProcList.rest; dynaport.countcycle _ 0; }; Jump: SimpleProc ~ { <> label: ATOM _ NARROW[params.first]; dynaport.testProcList _ NARROW[Atom.GetProp[$Simul2Sender, $PKList]]; WHILE dynaport.testProcList.first # label DO NextLine[dynaport]; ENDLOOP; }; B: PROC [b: BOOL] RETURNS [rb: REF ANY] = {rb _ NEW[BOOL _ b]}; <> <<>> WaitSync: SimpleProc ~ { <> Flag: ATOM _ NARROW[params.first]; Cond: BOOL ; IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond _ FALSE ELSE Cond _ NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^; IF Cond THEN NextLine[dynaport]; }; SkipIfTrue: SimpleProc ~ { <> Flag: ATOM _ NARROW[params.first]; Cond: BOOL; IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond _ FALSE ELSE Cond _ NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^; NextLine[dynaport]; IF Cond THEN NextLine[dynaport]; }; SetFlag: SimpleProc ~ { <> Flag: ATOM _ NARROW[params.first]; Atom.PutProp[$Sync,Flag, B[TRUE]]; NextLine[dynaport]; }; ClearFlag: SimpleProc ~ { <> Flag: ATOM _ NARROW[params.first]; Atom.PutProp[$Sync,Flag, B[FALSE]]; NextLine[dynaport]; }; Wait: SimpleProc ~ { <> countcycle: CARD _ NARROW[params.first, REF CARD]^; IF dynaport.countcycle < countcycle THEN dynaport.countcycle _ dynaport.countcycle + 1 ELSE NextLine[dynaport]; }; WaitMsgSent: SimpleProc ~ { <> IF dynaport.status[MsgSent] = H THEN NextLine[dynaport]; }; WaitMsgReceived: SimpleProc ~ { <> <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle =1 THEN { dynaport.countcycle _ 2} ELSE IF dynaport.countcycle=2 THEN { dynaport.load _ H; dynaport.rqlar[ClrMsgHere] _ L; dynaport.countcycle _ 3 } ELSE IF dynaport.countcycle=3 THEN { dynaport.load _ L; NextLine[dynaport] }; }; Init: SimpleProc ~ { <> Ports.LCToLS[0,dynaport.rqlar]; Ports.LCToLS[0,dynaport.sendpar]; dynaport.send _ H; -- for this version send is not useful (only for DbugBus) Ports.LCToLS[0,dynaport.alpha]; Ports.LCToLS[11111111H,dynaport.beta]; Ports.LCToLS[22222222H,dynaport.gama]; Ports.LCToLS[33333333H,dynaport.delta]; Ports.LCToLS[44444444H,dynaport.epsilon]; IF dynaport.countcycle<4 THEN { dynaport.countcycle _ dynaport.countcycle+1; dynaport.load _ H } ELSE { dynaport.countcycle _ 0; dynaport.load _ L }; NextLine[dynaport]; }; ReceiveAll:SimpleProc~ { <> dynaport.sendpar[AllMsg] _ H; dynaport.sendpar[AnyId] _ H; IF dynaport.countcycle<4 THEN { dynaport.countcycle _ dynaport.countcycle+1; dynaport.load _ H } ELSE { dynaport.countcycle _ 0; dynaport.load _ L }; NextLine[dynaport]; }; StartStop: SimpleProc ~ { SELECT dynaport.countcycle FROM <5 => { dynaport.rqlar[bitStop] _ L; dynaport.countcycle _ dynaport.countcycle+1; dynaport.load_ H }; IN [5..36] => { dynaport.rqlar[bitStop] _ H; dynaport.rqlar[ClrMsgHere] _ H; dynaport.countcycle _ dynaport.countcycle+1; dynaport.load_ H}; IN [37..40] => { dynaport.rqlar[bitStop] _ L; dynaport.rqlar[ClrMsgHere] _ L; dynaport.countcycle _ dynaport.countcycle+1}; ENDCASE => { dynaport.load _ L; NextLine[dynaport] }; }; convbits: PROC [data: CARDINAL] RETURNS [dataasbits: WordAsBits] ~ { dataasbits _ LOOPHOLE[data] }; cvcardbits: PROC [data: CARD] RETURNS [dataasbits: DWAsBits] ~ { dataasbits _ LOOPHOLE[Basics.SwapHalves[LOOPHOLE[data]]] }; MakeHeader: PROC [dynaport: Dyn.DynaPortState, cmd: Cmd, mode: ModeError _ TRUE, sh: Shared _ FALSE, id: DeviceID _ 0, add: Address _ qZero] RETURNS [] ~ { header: Quad; header _ qZero; header _ DynaBusInterface.InsertCmd[header, cmd]; header _ DynaBusInterface.InsertModeError[header, mode]; header _ DynaBusInterface.InsertShared[header, sh]; header _ DynaBusInterface.InsertDeviceID[header, id]; header _ DynaBusInterface.InsertAddress[header, add]; dynaport.alpha[0] _ H; -- For the Header dynaport.alpha[1] _ L; -- For the Parity dynaport.alpha[2] _ L; -- For Spare dynaport.alpha[3] _ L; -- For Spare FOR bit: NAT IN [4..20) DO dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[0]][bit-4]]; ENDLOOP; FOR bit: NAT IN [20..36) DO dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[1]][bit-20]]; ENDLOOP; FOR bit: NAT IN [36..52) DO dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[2]][bit-36]]; ENDLOOP; FOR bit: NAT IN [52..68) DO dynaport.alpha[bit] _ Ports.ToLevel[convbits[header[3]][bit-52]]; ENDLOOP; }; MakeData1: PROC [dynaport: Dyn.DynaPortState, d0: Quad] RETURNS [] ~ { <> <<>> FOR bit: NAT IN [0..4) DO <> dynaport.beta[bit] _ L; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; FOR bit: NAT IN [4..20) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[0]][bit-4]]; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; FOR bit: NAT IN [20..36) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[1]][bit-20]]; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; FOR bit: NAT IN [36..52) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[2]][bit-36]]; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; FOR bit: NAT IN [52..68) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[3]][bit-52]]; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; }; MakeData4: PROC [dynaport: Dyn.DynaPortState, d0,d1,d2,d3: Quad] RETURNS [] ~ { <> <<>> FOR bit: NAT IN [0..4) DO <> dynaport.beta[bit] _ L; dynaport.gama[bit] _ L; dynaport.delta[bit] _ L; dynaport.epsilon[bit] _ L; ENDLOOP; FOR bit: NAT IN [4..20) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[0]][bit-4]]; dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[0]][bit-4]]; dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[0]][bit-4]]; dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[0]][bit-4]]; ENDLOOP; FOR bit: NAT IN [20..36) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[1]][bit-20]]; dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[1]][bit-20]]; dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[1]][bit-20]]; dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[1]][bit-20]]; ENDLOOP; FOR bit: NAT IN [36..52) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[2]][bit-36]]; dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[2]][bit-36]]; dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[2]][bit-36]]; dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[2]][bit-36]]; ENDLOOP; FOR bit: NAT IN [52..68) DO dynaport.beta[bit] _ Ports.ToLevel[convbits[d0[3]][bit-52]]; dynaport.gama[bit] _ Ports.ToLevel[convbits[d1[3]][bit-52]]; dynaport.delta[bit] _ Ports.ToLevel[convbits[d2[3]][bit-52]]; dynaport.epsilon[bit] _ Ports.ToLevel[convbits[d3[3]][bit-52]]; ENDLOOP; }; SetRQL: PROC [dynaport: Dyn.DynaPortState, rq: Requestype, lg: LengthCom] RETURNS [] ~ { <> SELECT rq FROM Nop => {dynaport.rqlar[0] _ L; dynaport.rqlar[1] _ L}; Hold => {dynaport.rqlar[0] _ L; dynaport.rqlar[1] _ H}; Lowp => {dynaport.rqlar[0] _ H; dynaport.rqlar[1] _ L}; Highp => {dynaport.rqlar[0] _ H; dynaport.rqlar[1] _ H}; ENDCASE => ERROR; dynaport.rqlar[2] _ IF lg=Short THEN L ELSE H; }; CheckRcvCom: PROC [dynaport: Dyn.DynaPortState, cmd: Cmd] RETURNS [r: BOOL] ~ { <> val:CARD _ 0; val _ val + (IF dynaport.ialpha[8]=L THEN 0 ELSE 1); val _ val + (IF dynaport.ialpha[7]=L THEN 0 ELSE 2); val _ val + (IF dynaport.ialpha[6]=L THEN 0 ELSE 4); val _ val + (IF dynaport.ialpha[5]=L THEN 0 ELSE 8); val _ val + (IF dynaport.ialpha[4]=L THEN 0 ELSE 16); r _ val=ORD[cmd] }; CheckRcvData0: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ { <> d0: Quad; par1: LIST OF REF ANY _ params; d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; r _ TRUE; FOR bit: NAT IN [36..52) DO IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [52..68) DO IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE; ENDLOOP; }; CheckRcvData1: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ { <> d0,d1: Quad; par1: LIST OF REF ANY _ params; d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; d1 _ NARROW[par1.first, REF Quad]^; r _ TRUE; FOR bit: NAT IN [4..20) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [20..36) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [36..52) DO IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE; IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [52..68) DO IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE; IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r _ FALSE; ENDLOOP; }; CheckRcvData4: PROC [dynaport: Dyn.DynaPortState, params: LIST OF REF ANY _ NIL ] RETURNS [r: BOOL] ~ { <> d0, d1, d2, d3: Quad; par1: LIST OF REF ANY _ params; d0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; d1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; d2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; d3 _ NARROW[par1.first, REF Quad]^; r _ TRUE; FOR bit: NAT IN [4..20) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[0]][bit-4]] THEN r _ FALSE; IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r _ FALSE; IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[0]][bit-4]] THEN r _ FALSE; IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[0]][bit-4]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [20..36) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[1]][bit-20]] THEN r _ FALSE; IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r _ FALSE; IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[1]][bit-20]] THEN r _ FALSE; IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[1]][bit-20]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [36..52) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r _ FALSE; IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r _ FALSE; IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[2]][bit-36]] THEN r _ FALSE; IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[2]][bit-36]] THEN r _ FALSE; ENDLOOP; FOR bit: NAT IN [52..68) DO IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r _ FALSE; IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r _ FALSE; IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[3]][bit-52]] THEN r _ FALSE; IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[3]][bit-52]] THEN r _ FALSE; ENDLOOP; }; SendRequest: SimpleProc~ { <> SELECT dynaport.countcycle FROM 0 => { dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[bitSend] _ H; --bit send dynaport.load _ H; }; 1 => { dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[bitSend] _ H }; 2 => { dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[bitSend] _ L }; ENDCASE => {dynaport.countcycle _ dynaport.countcycle+1; dynaport.load _ L; NextLine[dynaport] }; }; <> <<>> <<>> <<>> <<>> WriteBlockRqst : SimpleProc~ { <> <<"address" is the first parameter, "data" is the second>> <<>> data0, data1, data2, data3: Quad; address: Quad _ NARROW[params.first, REF Quad]^; par1: LIST OF REF ANY _ params.rest; data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data3 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Highp, Long]; MakeHeader[dynaport: dynaport,cmd: WBRqst, add: address, mode: TRUE]; MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3]; SendRequest[dynaport] }; FlushBlockRqst : SimpleProc~ { <> <<"address" is the first parameter, "data" is the second>> <<>> data0, data1, data2, data3: Quad; address: Quad _ NARROW[params.first, REF Quad]^; par1: LIST OF REF ANY _ params.rest; data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data3 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Highp, Long]; MakeHeader[dynaport: dynaport,cmd: FBRqst, add: address, mode: TRUE]; MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3]; SendRequest[dynaport] }; ReadBlockRqst: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: RBRqst, add: address, mode: TRUE]; MakeData1[dynaport: dynaport, d0: [0,0,0,0] ]; SendRequest[dynaport] }; ReadBlockRply : SimpleProc~ { <> <<"address" is the first parameter, "data" is the second>> <<>> data0, data1, data2, data3: Quad; address: Quad _ NARROW[params.first, REF Quad]^; par1: LIST OF REF ANY _ params.rest; data0 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF Quad]^; par1 _ par1.rest; data3 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Highp, Long]; MakeHeader[dynaport: dynaport,cmd: RBRply, add: address, mode: TRUE]; MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3]; SendRequest[dynaport] }; WriteSingleRqst: SimpleProc ~ { <> <<>> data0, address : Quad; par1: LIST OF REF ANY _ params.rest; address _ NARROW[params.first, REF Quad]^; data0 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: WSRqst, add: address, mode: TRUE]; MakeData1[dynaport: dynaport, d0: data0 ]; SendRequest[dynaport] }; CondWSRqst: SimpleProc ~ { <> <<>> data0, address : Quad; par1: LIST OF REF ANY _ params.rest; address _ NARROW[params.first, REF Quad]^; data0 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: CWSRqst, add: address, mode: TRUE]; MakeData1[dynaport: dynaport, d0: data0 ]; SendRequest[dynaport] }; CondWSRply: SimpleProc ~ { <> <<>> data0, address : Quad; id: DeviceID; data0 _ NARROW[params.first, REF Quad]^; SetRQL[dynaport, Highp, Long]; address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..68) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE]; MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0]; SendRequest[dynaport] }; CondWSRply1: SimpleProc ~ { <> <<>> data0, address : Quad; address _ NARROW[params.first, REF Quad]^; data0 _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Highp, Long]; MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE]; MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0]; SendRequest[dynaport] }; DeMapRqst: SimpleProc ~ { <> <<>> data0, address : Quad; par1: LIST OF REF ANY _ params.rest; address _ NARROW[params.first, REF Quad]^; data0 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: DeMapRqst, add: address, mode: TRUE]; MakeData1[dynaport: dynaport, d0: data0 ]; SendRequest[dynaport] }; DeMapRply: SimpleProc ~ { <> <<>> address : Quad; id: DeviceID; data: Quad _ NARROW[params.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..68) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; MakeHeader[dynaport: dynaport,cmd: DeMapRply, id: id, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data]; SendRequest[dynaport] }; DeMapRply1: SimpleProc ~ { <> <<>> data0, address : Quad; par1: LIST OF REF ANY _ params.rest; address _ NARROW[params.first, REF Quad]^; data0 _ NARROW[par1.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. MakeHeader[dynaport: dynaport,cmd: DeMapRply, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data0]; SendRequest[dynaport] }; WriteSingleRply: SimpleProc ~ { <> <<>> address : Quad; id: DeviceID; data: Quad _ NARROW[params.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..68) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; MakeHeader[dynaport: dynaport,cmd: WSRply, id: id, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data]; SendRequest[dynaport] }; WriteSingleRply1: SimpleProc ~ { <> <<>> address,data : Quad; address _ NARROW[params.first, REF Quad]^; data _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. MakeHeader[dynaport: dynaport,cmd: WSRply, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data]; SendRequest[dynaport] }; MapRqst: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; aid: Quad _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport, cmd: MapRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: aid]; SendRequest[dynaport]; }; MapReply: SimpleProc ~ { <> <<>> address: Quad; flags: CARD; id: DeviceID; flags _ NARROW[params.first, REF CARD]^; SetRQL[dynaport, Lowp, Short]; address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..64) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[64..68) DO address[3] _ address[3]*2 + (IF (cvcardbits[flags][bit-64+28]) THEN 1 ELSE 0); --Flags ENDLOOP; MakeHeader[dynaport: dynaport,cmd: MapRply, id: id, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: [0,0,0,0]]; SendRequest[dynaport] }; IOWriteRqst: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; data: Quad _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data]; SendRequest[dynaport] }; IOWriteRply: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; data: Quad _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. MakeHeader[dynaport: dynaport,cmd: IOWRply, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: data]; SendRequest[dynaport] }; IOWriteRply0: SimpleProc ~ { <> <<>> address: Quad; id: DeviceID; SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short. address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..68) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; MakeHeader[dynaport: dynaport,cmd: IOWRply, id: id, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: [0,0,0,0]]; SendRequest[dynaport] }; IOReadRqst: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: IORRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: [0,0,0,0] ]; SendRequest[dynaport] }; IOReadRply: SimpleProc ~ { <> <<>> address: Quad _ NARROW[params.first, REF Quad]^; data: Quad _ NARROW[params.rest.first, REF Quad]^; SetRQL[dynaport, Lowp, Short]; MakeHeader[dynaport: dynaport,cmd: IORRply, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: data ]; SendRequest[dynaport] }; IOReadRply0: SimpleProc ~ { <> <<>> data: Quad _ NARROW[params.first, REF Quad]^; address: Quad; id: DeviceID; SetRQL[dynaport, Lowp, Short]; address[0] _ 0; address[1] _ 0; address[2] _ 0; address[3] _ 0; id _ 0; FOR bit: NAT IN[11..21) DO id _ id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[36..52) DO address[2] _ address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; FOR bit: NAT IN[52..68) DO address[3] _ address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1); ENDLOOP; MakeHeader[dynaport: dynaport,cmd: IORRply, id: id, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: data ]; SendRequest[dynaport] }; WaitReply: SimpleProc ~ { <> <> << if yes goto Nextline, if not wait an another message>> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF dynaport.ialpha[8]=H THEN NextLine[dynaport] ELSE dynaport.countcycle _ 0; } } }; WaitMapRqst: SimpleProc ~ { <> <> << if yes goto Nextline, if not wait an another message>> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, MapRqst] THEN NextLine[dynaport] ELSE dynaport.countcycle _ 0; --wait a new message } } }; WaitReadBlockRplyandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, RBRply] THEN { IF ~CheckRcvData4[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data4"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message } } }; WaitIOReadRplyandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, IORRply] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitIOWRplyandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, IOWRply] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitIOWRqstandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, IOWRqst] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitIOReadRqstandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, IORRqst] THEN { IF ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitReadBlockRqstandCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, RBRqst] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitReadBlockRqstandCheck1: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, RBRqst] THEN { IF ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitWriteSingleRqstAndCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, WSRqst] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitCondWriteSingleRqstAndCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, CWSRqst] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; WaitCondWriteSingleRplyAndCheck: SimpleProc ~ { <> <<>> IF dynaport.status[MsgHere] = H AND dynaport.countcycle =0 THEN { dynaport.countcycle _ 1; dynaport.rqlar[ClrMsgHere] _ H; dynaport.load _ H } ELSE IF dynaport.countcycle=1 THEN dynaport.countcycle _2 ELSE { IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6) --for wait all the message THEN{ dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[ClrMsgHere] _ L } ELSE IF dynaport.countcycle=6 THEN{ dynaport.load _ L; IF CheckRcvCom[dynaport, CWSRply] THEN { IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"]; NextLine[dynaport]} ELSE dynaport.countcycle _ 0; --wait a new message }; } }; <> <<>> <<>> IOWrite0 : SimpleProc~ { <> <> <<>> <<>> data, data0, data3, data4, data5, data6, data7, data8: CARD; data1, data2: BOOL; address: Quad _ [0,0,30H,0400H]; par1: LIST OF REF ANY _ params; data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF BOOL]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF BOOL]^; par1 _ par1.rest; data3 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data4 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data5 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data6 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data7 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data8 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; SetRQL[dynaport, Lowp, Short]; data_ MCUtils.ComposeIOWrite0[ownerFifoDelay: data0, enbCorr: data1, enbOpReflect: data2, selRefCk: data3, gntDelay: data4, pchgDelay: data5, refDelay: data6, wrDelay: data7, rdDelay: data8]; MakeHeader[dynaport: dynaport, cmd: IOWRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data],Basics.LowHalf[data]] ]; SendRequest[dynaport] }; IOWrite1 : SimpleProc~ { <> <> <<>> <<>> data, data0, data1, data2, data3 : CARD; address: Quad _ [0,0,30H,0401H]; par1: LIST OF REF ANY _ params; data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data3 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; SetRQL[dynaport, Lowp, Short]; data _ MCUtils.ComposeIOWrite1[banks: data0, ramAddWires: data1, bankAdd: data2, pageAdd: data3]; MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport,d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]]; SendRequest[dynaport] }; IOWrite2 : SimpleProc~ { <> <> <<>> data, data0, data1, data2 : CARD; address: Quad _ [0,0,30H,0402H]; par1: LIST OF REF ANY _ params; data0 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data1 _ NARROW[par1.first, REF CARD]^; par1 _ par1.rest; data2 _ NARROW[par1.first, REF CARD]^; SetRQL[dynaport, Lowp, Short]; data_ MCUtils.ComposeIOWrite2[banks: data0, ramAddWires: data1, bankAdd: data2]; MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE]; MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]]; SendRequest[dynaport] }; SendShOw : SimpleProc~ { <> <> <<>> SO: Rope.ROPE _ NARROW[params.first, REF Rope.ROPE]^; SELECT dynaport.countcycle FROM 0 => { dynaport.countcycle _ dynaport.countcycle+1; SELECT TRUE FROM Rope.Equal[SO, "S"] => dynaport.rqlar[bitShared] _ H; --bit Shared Rope.Equal[SO, "O"] => dynaport.rqlar[bitOwner] _ H; --bit bitOwner Rope.Equal[SO, "SO"] => {dynaport.rqlar[bitOwner] _ H; dynaport.rqlar[bitShared]_ H}; ENDCASE => ERROR; dynaport.load _ H; }; 1 => { dynaport.countcycle _ dynaport.countcycle+1; dynaport.rqlar[bitShared] _ L; dynaport.rqlar[bitOwner] _ L}; ENDCASE => {dynaport.countcycle _ dynaport.countcycle+1; dynaport.load _ L; NextLine[dynaport] }; }; <<>> <<>> C: PROC [c: CARD] RETURNS [rc: REF ANY] = {rc _ NEW[CARD _ c]}; Q: PROC [c: Quad] RETURNS [rc: REF ANY] = {rc _ NEW[Quad _ c]}; <> SendBus: PUBLIC PROC [dynaport: Dyn.DynaPortState] RETURNS [] ~ { IF dynaport.testProcList = NIL THEN { dynaport.testProcList _ NARROW[Atom.GetProp[$Simul2Sender, $PKList]]; }; DO AtomDidSomething: PROC [atom: ATOM, params: LIST OF REF ANY] RETURNS [BOOL] = { v: REF ANY = Atom.GetProp[$Simul2Sender, atom]; IF v # NIL THEN { spr: REF SimpleProc = NARROW[v]; spr^[dynaport, params]; RETURN[TRUE]; } ELSE { NextLine[dynaport]; RETURN[FALSE]; }; }; WITH dynaport.testProcList.first SELECT FROM atom: ATOM => IF AtomDidSomething[atom, NIL] THEN EXIT; list: LIST OF REF ANY => { WITH list.first SELECT FROM atom: ATOM => IF AtomDidSomething[atom, list.rest] THEN EXIT; ENDCASE => ERROR; }; ENDCASE => ERROR; ENDLOOP; }; Atom.PutProp[$Simul2Sender, $Init, NEW[SimpleProc _ Init]]; Atom.PutProp[$Simul2Sender, $ReceiveAll, NEW[SimpleProc _ ReceiveAll]]; Atom.PutProp[$Simul2Sender, $StartStop, NEW[SimpleProc _ StartStop]]; Atom.PutProp[$Simul2Sender, $Wait, NEW[SimpleProc _ Wait]]; Atom.PutProp[$Simul2Sender, $WaitMsgSent, NEW[SimpleProc _ WaitMsgSent]]; Atom.PutProp[$Simul2Sender, $WaitMsgReceived, NEW[SimpleProc _ WaitMsgReceived]]; Atom.PutProp[$Simul2Sender, $Jump, NEW[SimpleProc _ Jump]]; Atom.PutProp[$Simul2Sender, $WaitSync, NEW[SimpleProc _ WaitSync]]; Atom.PutProp[$Simul2Sender, $SetFlag, NEW[SimpleProc _ SetFlag]]; Atom.PutProp[$Simul2Sender, $ClearFlag, NEW[SimpleProc _ ClearFlag]]; Atom.PutProp[$Simul2Sender, $SkipIfTrue, NEW[SimpleProc _ SkipIfTrue]]; Atom.PutProp[$Simul2Sender, $StopSimul, NEW[SimpleProc _ StopSimul]]; <> Atom.PutProp[$Simul2Sender, $WriteBlockRqst, NEW[SimpleProc _ WriteBlockRqst]]; Atom.PutProp[$Simul2Sender, $ReadBlockRqst, NEW[SimpleProc _ ReadBlockRqst]]; Atom.PutProp[$Simul2Sender, $ReadBlockRply, NEW[SimpleProc _ ReadBlockRply]]; Atom.PutProp[$Simul2Sender, $WriteSingleRqst, NEW[SimpleProc _ WriteSingleRqst]]; Atom.PutProp[$Simul2Sender, $WriteSingleRply, NEW[SimpleProc _ WriteSingleRply]]; Atom.PutProp[$Simul2Sender, $WriteSingleRply1, NEW[SimpleProc _ WriteSingleRply1]]; Atom.PutProp[$Simul2Sender, $FlushBlockRqst, NEW[SimpleProc _ FlushBlockRqst]]; Atom.PutProp[$Simul2Sender, $CondWSRqst, NEW[SimpleProc _ CondWSRqst]]; Atom.PutProp[$Simul2Sender, $CondWSRply, NEW[SimpleProc _ CondWSRply]]; Atom.PutProp[$Simul2Sender, $CondWSRply1, NEW[SimpleProc _ CondWSRply1]]; Atom.PutProp[$Simul2Sender, $DeMapRqst, NEW[SimpleProc _ DeMapRqst]]; Atom.PutProp[$Simul2Sender, $DeMapRply, NEW[SimpleProc _ DeMapRply]]; Atom.PutProp[$Simul2Sender, $DeMapRply1, NEW[SimpleProc _ DeMapRply1]]; Atom.PutProp[$Simul2Sender, $WaitMapRqst, NEW[SimpleProc _ WaitMapRqst]]; Atom.PutProp[$Simul2Sender, $MapReply, NEW[SimpleProc _ MapReply]]; Atom.PutProp[$Simul2Sender, $IOReadRqst, NEW[SimpleProc _ IOReadRqst]]; Atom.PutProp[$Simul2Sender, $IOReadRply, NEW[SimpleProc _ IOReadRply]]; Atom.PutProp[$Simul2Sender, $IOReadRply0, NEW[SimpleProc _ IOReadRply0]]; Atom.PutProp[$Simul2Sender, $MapRqst, NEW[SimpleProc _ MapRqst]]; Atom.PutProp[$Simul2Sender, $IOWriteRqst, NEW[SimpleProc _ IOWriteRqst]]; Atom.PutProp[$Simul2Sender, $IOWriteRply, NEW[SimpleProc _ IOWriteRply]]; Atom.PutProp[$Simul2Sender, $IOWriteRply0, NEW[SimpleProc _ IOWriteRply0]]; Atom.PutProp[$Simul2Sender, $WaitReply, NEW[SimpleProc _ WaitReply]]; Atom.PutProp[$Simul2Sender, $WaitReadBlockRplyandCheck, NEW[SimpleProc _ WaitReadBlockRplyandCheck]]; Atom.PutProp[$Simul2Sender, $WaitIOReadRplyandCheck, NEW[SimpleProc _ WaitIOReadRplyandCheck]]; Atom.PutProp[$Simul2Sender, $WaitIOWRplyandCheck, NEW[SimpleProc _ WaitIOWRplyandCheck]]; Atom.PutProp[$Simul2Sender, $WaitIOWRqstandCheck, NEW[SimpleProc _ WaitIOWRqstandCheck]]; Atom.PutProp[$Simul2Sender, $WaitIOReadRqstandCheck, NEW[SimpleProc _ WaitIOReadRqstandCheck]]; Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck, NEW[SimpleProc _ WaitReadBlockRqstandCheck]]; Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck1, NEW[SimpleProc _ WaitReadBlockRqstandCheck1]]; Atom.PutProp[$Simul2Sender, $WaitWriteSingleRqstAndCheck, NEW[SimpleProc _ WaitWriteSingleRqstAndCheck]]; Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRqstAndCheck, NEW[SimpleProc _ WaitCondWriteSingleRqstAndCheck]]; Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRplyAndCheck, NEW[SimpleProc _ WaitCondWriteSingleRplyAndCheck]]; <> Atom.PutProp[$Simul2Sender, $IOWrite0, NEW[SimpleProc _ IOWrite0]]; Atom.PutProp[$Simul2Sender, $IOWrite1, NEW[SimpleProc _ IOWrite1]]; Atom.PutProp[$Simul2Sender, $IOWrite2, NEW[SimpleProc _ IOWrite2]]; Atom.PutProp[$Simul2Sender, $SendShOw, NEW[SimpleProc _ SendShOw]]; Atom.PutProp[$Simul2Sender, $PKList, LIST[ $Init, $Nop, LIST[$Jump, $Nop] ]]; <<>> END. <<>> <<>> <> <<>> <<4-28-88: Change IOAddress of IOWrite0, IOWrite1, and IOWrite2 to be consistent with having the Memory Controller have DynaBusId=1 (not 0).>> <<4-29-88: Added $IOWriteRply command. JHH.>> <<>> <<>>