Simul2SenderImpl.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Created by Jean Gastinel, July 10, 1988 1:30:06 pm PDT
Hoel, April 29, 1988 5:21:37 pm PDT
Pradeep Sindhu May 5, 1988 7:39:04 pm PDT
DIRECTORY
Atom, Basics, BitOps, Dyn, DynaBusInterface, MCUtils, Ports, Rope, Simul2Sender;
Simul2SenderImpl: CEDAR PROGRAM
IMPORTS Atom, Basics, DynaBusInterface, MCUtils, Ports, Rope
EXPORTS Simul2Sender
Service Types
DynaBusEvent: SIGNAL [msg: Rope.ROPE]= CODE;
Requestype: TYPE = {Nop,Hold,Lowp,Highp};
LengthCom: TYPE = {Short,Long};
ReplyBit: TYPE = DynaBusInterface.ReplyCmdField;
Quad: TYPE = DynaBusInterface.Quad;
Cmd: TYPE = DynaBusInterface.Cmd;
ModeError: TYPE = DynaBusInterface.ModeError;
Shared: TYPE = DynaBusInterface.Shared;
DeviceID: TYPE = DynaBusInterface.DeviceID;
Address: TYPE = DynaBusInterface.Address;
qZero: Quad = BitOps.BitQWordZero;
WordAsBits: TYPE = PACKED ARRAY [0..16) OF BOOL;
DWAsBits: TYPE = PACKED ARRAY [0..32) OF BOOL;
SimpleProc: TYPE = PROC[dynaport: Dyn.DynaPortState, params: LIST OF REF ANY ← NIL ] RETURNS [];
HARDWARE DEFINITIONS
Definition of the register rqlar
bitSend: NAT=5;
bitStop: NAT=6;
bitShared: NAT=7;
bitOwner: NAT=8;
ClrMsgHere: NAT=9;
Definition of the Status register
MsgSent: NAT = 0; -- this bit is set when a message has been sent
MsgHere: NAT = 1; -- this bit is set when a message is received
Definition of the RecPar register
AllMsg: NAT = 13;
AnyId: NAT= 14;
Service Procs
StopSimul: SimpleProc ~ {
SIGNAL DynaBusEvent["End of Simulation"];
NextLine[dynaport];
};
NextLine: SimpleProc ~ {
dynaport.testProcList ← dynaport.testProcList.rest;
dynaport.countcycle ← 0;
};
Jump: SimpleProc ~ {
Jump to cycle line number : lnb
label: ATOM ← NARROW[params.first];
dynaport.testProcList ← NARROW[Atom.GetProp[$Simul2Sender, $PKList]];
WHILE dynaport.testProcList.first # label
DO
NextLine[dynaport];
ENDLOOP;
};
B: PROC [b: BOOL] RETURNS [rb: REF ANY] = {rb ← NEW[BOOL ← b]};
Interprocess Synchronisation
WaitSync: SimpleProc ~ {
This proc is use for synchronisation. It tests the value of a parameter atom $Flag
Flag: ATOM ← NARROW[params.first];
Cond: BOOL ;
IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond ← FALSE
ELSE Cond ← NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^;
IF Cond THEN NextLine[dynaport];
};
SkipIfTrue: SimpleProc ~ {
This proc is used for synchronisation. It tests the value of the parameter atom $Flag.
If the parameter is True, the next instruction is skiped. If it is Not True the
following instructions are normally executed.
Flag: ATOM ← NARROW[params.first];
Cond: BOOL;
IF Atom.GetProp[$Sync,Flag]=NIL THEN Cond ← FALSE
ELSE Cond ← NARROW[Atom.GetProp[$Sync,Flag],REF BOOL]^;
NextLine[dynaport];
IF Cond THEN NextLine[dynaport];
};
SetFlag: SimpleProc ~ {
This proc is use for synchronisation. It Set the value of a parameter atom $Flag
to TRUE
Flag: ATOM ← NARROW[params.first];
Atom.PutProp[$Sync,Flag, B[TRUE]];
NextLine[dynaport];
};
ClearFlag: SimpleProc ~ {
This proc is use for synchronisation. It Clears the value of a parameter atom $Flag
to FALSE
Flag: ATOM ← NARROW[params.first];
Atom.PutProp[$Sync,Flag, B[FALSE]];
NextLine[dynaport];
};
Wait: SimpleProc ~ {
This proc count "countcycle" cycle before going to the next instruction
countcycle: CARD ← NARROW[params.first, REF CARD]^;
IF dynaport.countcycle < countcycle
THEN dynaport.countcycle ← dynaport.countcycle + 1
ELSE NextLine[dynaport];
};
WaitMsgSent: SimpleProc ~ {
This proc tests the bit "MsgSent" of status, if it is H goto Nextline
IF dynaport.status[MsgSent] = H THEN NextLine[dynaport];
};
WaitMsgReceived: SimpleProc ~ {
This proc tests the bit "MsgHere" of status, if it is H goto Nextline
After clear this bit in setting and resetting the bit "ClrMsgHere" of the rqlar register
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle =1
THEN {
dynaport.countcycle ← 2}
ELSE
IF dynaport.countcycle=2
THEN {
dynaport.load ← H;
dynaport.rqlar[ClrMsgHere] ← L;
dynaport.countcycle ← 3 }
ELSE
IF dynaport.countcycle=3
THEN {
dynaport.load ← L;
NextLine[dynaport] };
};
Init: SimpleProc ~ {
This proc initialise the dynaport
Ports.LCToLS[0,dynaport.rqlar];
Ports.LCToLS[0,dynaport.sendpar];
dynaport.send ← H; -- for this version send is not useful (only for DbugBus)
Ports.LCToLS[0,dynaport.alpha];
Ports.LCToLS[11111111H,dynaport.beta];
Ports.LCToLS[22222222H,dynaport.gama];
Ports.LCToLS[33333333H,dynaport.delta];
Ports.LCToLS[44444444H,dynaport.epsilon];
IF dynaport.countcycle<4
THEN
{ dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load ← H }
ELSE
{ dynaport.countcycle ← 0;
dynaport.load ← L };
NextLine[dynaport];
};
ReceiveAll:SimpleProc~ {
This proc initialise the "sendpar" for receiving all the messages with any identifier
dynaport.sendpar[AllMsg] ← H;
dynaport.sendpar[AnyId] ← H;
IF dynaport.countcycle<4
THEN
{ dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load ← H }
ELSE
{ dynaport.countcycle ← 0;
dynaport.load ← L };
NextLine[dynaport];
};
StartStop: SimpleProc ~ {
SELECT dynaport.countcycle
FROM
<5 => {
dynaport.rqlar[bitStop] ← L;
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load← H };
IN [5..36] => {
dynaport.rqlar[bitStop] ← H;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load← H};
IN [37..40] => {
dynaport.rqlar[bitStop] ← L;
dynaport.rqlar[ClrMsgHere] ← L;
dynaport.countcycle ← dynaport.countcycle+1};
ENDCASE => {
dynaport.load ← L;
NextLine[dynaport] };
};
convbits:
PROC [data:
CARDINAL]
RETURNS [dataasbits: WordAsBits] ~ {
dataasbits ← LOOPHOLE[data]
};
cvcardbits:
PROC [data:
CARD]
RETURNS [dataasbits: DWAsBits] ~ {
dataasbits ← LOOPHOLE[Basics.SwapHalves[LOOPHOLE[data]]]
};
MakeHeader:
PROC [dynaport: Dyn.DynaPortState, cmd: Cmd, mode: ModeError ←
TRUE, sh: Shared ←
FALSE, id: DeviceID ← 0, add: Address ← qZero]
RETURNS [] ~ {
header: Quad;
header ← qZero;
header ← DynaBusInterface.InsertCmd[header, cmd];
header ← DynaBusInterface.InsertModeError[header, mode];
header ← DynaBusInterface.InsertShared[header, sh];
header ← DynaBusInterface.InsertDeviceID[header, id];
header ← DynaBusInterface.InsertAddress[header, add];
dynaport.alpha[0] ← H; -- For the Header
dynaport.alpha[1] ← L; -- For the Parity
dynaport.alpha[2] ← L; -- For Spare
dynaport.alpha[3] ← L; -- For Spare
FOR bit: NAT
IN [4..20)
DO
dynaport.alpha[bit] ← Ports.ToLevel[convbits[header[0]][bit-4]];
ENDLOOP;
FOR bit: NAT
IN [20..36)
DO
dynaport.alpha[bit] ← Ports.ToLevel[convbits[header[1]][bit-20]];
ENDLOOP;
FOR bit: NAT
IN [36..52)
DO
dynaport.alpha[bit] ← Ports.ToLevel[convbits[header[2]][bit-36]];
ENDLOOP;
FOR bit: NAT
IN [52..68)
DO
dynaport.alpha[bit] ← Ports.ToLevel[convbits[header[3]][bit-52]];
ENDLOOP;
};
MakeData1:
PROC [dynaport: Dyn.DynaPortState, d0: Quad]
RETURNS [] ~ {
This proc builds a one 64-bits word of data
FOR bit: NAT
IN [0..4)
DO
i=0 for the Header, i=1 for the Parity, i=2 & 3 for Spare
dynaport.beta[bit] ← L;
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
FOR bit: NAT
IN [4..20)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[0]][bit-4]];
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
FOR bit: NAT
IN [20..36)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[1]][bit-20]];
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
FOR bit: NAT
IN [36..52)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[2]][bit-36]];
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
FOR bit: NAT
IN [52..68)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[3]][bit-52]];
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
};
MakeData4:
PROC [dynaport: Dyn.DynaPortState, d0,d1,d2,d3: Quad]
RETURNS [] ~ {
This proc builds four 64-bits words of data
FOR bit: NAT
IN [0..4)
DO
i=0 for the Header, i=1 for the Parity, i=2 & 3 for Spare
dynaport.beta[bit] ← L;
dynaport.gama[bit] ← L;
dynaport.delta[bit] ← L;
dynaport.epsilon[bit] ← L;
ENDLOOP;
FOR bit: NAT
IN [4..20)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[0]][bit-4]];
dynaport.gama[bit] ← Ports.ToLevel[convbits[d1[0]][bit-4]];
dynaport.delta[bit] ← Ports.ToLevel[convbits[d2[0]][bit-4]];
dynaport.epsilon[bit] ← Ports.ToLevel[convbits[d3[0]][bit-4]];
ENDLOOP;
FOR bit: NAT
IN [20..36)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[1]][bit-20]];
dynaport.gama[bit] ← Ports.ToLevel[convbits[d1[1]][bit-20]];
dynaport.delta[bit] ← Ports.ToLevel[convbits[d2[1]][bit-20]];
dynaport.epsilon[bit] ← Ports.ToLevel[convbits[d3[1]][bit-20]];
ENDLOOP;
FOR bit: NAT
IN [36..52)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[2]][bit-36]];
dynaport.gama[bit] ← Ports.ToLevel[convbits[d1[2]][bit-36]];
dynaport.delta[bit] ← Ports.ToLevel[convbits[d2[2]][bit-36]];
dynaport.epsilon[bit] ← Ports.ToLevel[convbits[d3[2]][bit-36]];
ENDLOOP;
FOR bit: NAT
IN [52..68)
DO
dynaport.beta[bit] ← Ports.ToLevel[convbits[d0[3]][bit-52]];
dynaport.gama[bit] ← Ports.ToLevel[convbits[d1[3]][bit-52]];
dynaport.delta[bit] ← Ports.ToLevel[convbits[d2[3]][bit-52]];
dynaport.epsilon[bit] ← Ports.ToLevel[convbits[d3[3]][bit-52]];
ENDLOOP;
};
SetRQL:
PROC [dynaport: Dyn.DynaPortState, rq: Requestype, lg: LengthCom]
RETURNS [] ~ {
This proc set the request bits and the length in the register SendPar
SELECT rq
FROM
Nop => {dynaport.rqlar[0] ← L; dynaport.rqlar[1] ← L};
Hold => {dynaport.rqlar[0] ← L; dynaport.rqlar[1] ← H};
Lowp => {dynaport.rqlar[0] ← H; dynaport.rqlar[1] ← L};
Highp => {dynaport.rqlar[0] ← H; dynaport.rqlar[1] ← H};
ENDCASE => ERROR;
dynaport.rqlar[2] ← IF lg=Short THEN L ELSE H;
};
CheckRcvCom:
PROC [dynaport: Dyn.DynaPortState, cmd: Cmd]
RETURNS [r:
BOOL] ~ {
This proc tests if the received command is cmd
val:CARD ← 0;
val ← val + (IF dynaport.ialpha[8]=L THEN 0 ELSE 1);
val ← val + (IF dynaport.ialpha[7]=L THEN 0 ELSE 2);
val ← val + (IF dynaport.ialpha[6]=L THEN 0 ELSE 4);
val ← val + (IF dynaport.ialpha[5]=L THEN 0 ELSE 8);
val ← val + (IF dynaport.ialpha[4]=L THEN 0 ELSE 16);
r ← val=ORD[cmd]
};
CheckRcvData0:
PROC [dynaport: Dyn.DynaPortState, params:
LIST
OF
REF
ANY ←
NIL ]
RETURNS [r:
BOOL] ~ {
This proc tests only that the address part of the received data equal the parameter
d0: Quad;
par1: LIST OF REF ANY ← params;
d0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
r ← TRUE;
FOR bit:
NAT
IN [36..52)
DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r ← FALSE;
ENDLOOP;
FOR bit:
NAT
IN [52..68)
DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r ← FALSE;
ENDLOOP;
};
CheckRcvData1:
PROC [dynaport: Dyn.DynaPortState, params:
LIST
OF
REF
ANY ←
NIL ]
RETURNS [r:
BOOL] ~ {
This proc tests if the received Data on one word equals the parameter
d0,d1: Quad;
par1: LIST OF REF ANY ← params;
d0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
d1 ← NARROW[par1.first, REF Quad]^;
r ← TRUE;
FOR bit: NAT
IN [4..20)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r ← FALSE;
ENDLOOP;
FOR bit: NAT
IN [20..36)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r ← FALSE;
ENDLOOP;
FOR bit:
NAT
IN [36..52)
DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r ← FALSE;
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r ← FALSE;
ENDLOOP;
FOR bit:
NAT
IN [52..68)
DO
IF dynaport.ialpha[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r ← FALSE;
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r ← FALSE;
ENDLOOP;
};
CheckRcvData4:
PROC [dynaport: Dyn.DynaPortState, params:
LIST
OF
REF
ANY ←
NIL ]
RETURNS [r:
BOOL] ~ {
This proc tests if the received Data on four words equals the parameter
d0, d1, d2, d3: Quad;
par1: LIST OF REF ANY ← params;
d0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
d1 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
d2 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
d3 ← NARROW[par1.first, REF Quad]^;
r ← TRUE;
FOR bit: NAT
IN [4..20)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[0]][bit-4]] THEN r ← FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[0]][bit-4]] THEN r ← FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[0]][bit-4]] THEN r ← FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[0]][bit-4]] THEN r ← FALSE;
ENDLOOP;
FOR bit: NAT
IN [20..36)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[1]][bit-20]] THEN r ← FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[1]][bit-20]] THEN r ← FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[1]][bit-20]] THEN r ← FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[1]][bit-20]] THEN r ← FALSE;
ENDLOOP;
FOR bit:
NAT
IN [36..52)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[2]][bit-36]] THEN r ← FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[2]][bit-36]] THEN r ← FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[2]][bit-36]] THEN r ← FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[2]][bit-36]] THEN r ← FALSE;
ENDLOOP;
FOR bit:
NAT
IN [52..68)
DO
IF dynaport.ibeta[bit] ~= Ports.ToLevel[convbits[d0[3]][bit-52]] THEN r ← FALSE;
IF dynaport.igama[bit] ~= Ports.ToLevel[convbits[d1[3]][bit-52]] THEN r ← FALSE;
IF dynaport.idelta[bit] ~= Ports.ToLevel[convbits[d2[3]][bit-52]] THEN r ← FALSE;
IF dynaport.iepsilon[bit] ~= Ports.ToLevel[convbits[d3[3]][bit-52]] THEN r ← FALSE;
ENDLOOP;
};
SendRequest: SimpleProc~ {
With the bit "load" active, this proc set and reset the bit "send"
SELECT dynaport.countcycle
FROM
0 => { dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[bitSend] ← H; --bit send
dynaport.load ← H; };
1 => { dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[bitSend] ← H };
2 => { dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[bitSend] ← L };
ENDCASE => {dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load ← L;
NextLine[dynaport] };
};
DynaBus Commands
WriteBlockRqst : SimpleProc~ {
This proc send a WriteBlock Request command at the address "address", with value "data"
"address" is the first parameter, "data" is the second
data0, data1, data2, data3: Quad;
address: Quad ← NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY ← params.rest;
data0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data3 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
MakeHeader[dynaport: dynaport,cmd: WBRqst, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};
FlushBlockRqst : SimpleProc~ {
This proc send a FlushBlockRqst command at the address "address", with value "data"
"address" is the first parameter, "data" is the second
data0, data1, data2, data3: Quad;
address: Quad ← NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY ← params.rest;
data0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data3 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
MakeHeader[dynaport: dynaport,cmd: FBRqst, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};
ReadBlockRqst: SimpleProc ~ {
This proc send a ReadBlock Request command at the address "address"
address: Quad ← NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: RBRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0] ];
SendRequest[dynaport]
};
ReadBlockRply : SimpleProc~ {
This proc send a ReadBlockRply command at the address "address", with value "data"
"address" is the first parameter, "data" is the second
data0, data1, data2, data3: Quad;
address: Quad ← NARROW[params.first, REF Quad]^;
par1: LIST OF REF ANY ← params.rest;
data0 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF Quad]^; par1 ← par1.rest;
data3 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
MakeHeader[dynaport: dynaport,cmd: RBRply, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data1, d2: data2, d3: data3];
SendRequest[dynaport]
};
WriteSingleRqst: SimpleProc ~ {
This proc send a WriteSingleRqst command at the address "address"
data0, address : Quad;
par1: LIST OF REF ANY ← params.rest;
address ← NARROW[params.first, REF Quad]^;
data0 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: WSRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]
};
CondWSRqst: SimpleProc ~ {
This proc send a CondWriteSingleRqst command at the address "address"
data0, address : Quad;
par1: LIST OF REF ANY ← params.rest;
address ← NARROW[params.first, REF Quad]^;
data0 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: CWSRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]
};
CondWSRply: SimpleProc ~ {
This proc send a CondWriteSingleRply command with the parameters of the previous command, exept the data
data0, address : Quad;
id: DeviceID;
data0 ← NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..68)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0];
SendRequest[dynaport]
};
CondWSRply1: SimpleProc ~ {
This proc send a CondWriteSingleRply command with the given parameters
data0, address : Quad;
address ← NARROW[params.first, REF Quad]^;
data0 ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Highp, Long];
MakeHeader[dynaport: dynaport,cmd: CWSRply, add: address, mode: TRUE];
MakeData4[dynaport: dynaport, d0: data0, d1: data0, d2: data0, d3: data0];
SendRequest[dynaport]
};
DeMapRqst: SimpleProc ~ {
This proc send a DeMapRqst command at the address "address"
data0, address : Quad;
par1: LIST OF REF ANY ← params.rest;
address ← NARROW[params.first, REF Quad]^;
data0 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: DeMapRqst, add: address, mode: TRUE];
MakeData1[dynaport: dynaport, d0: data0 ];
SendRequest[dynaport]
};
DeMapRply: SimpleProc ~ {
This proc send a DeMap Reply command with the previously received parameter
address : Quad;
id: DeviceID;
data: Quad ← NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..68)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: DeMapRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};
DeMapRply1: SimpleProc ~ {
This proc send a DeMap Reply command with the previously received parameter
data0, address : Quad;
par1: LIST OF REF ANY ← params.rest;
address ← NARROW[params.first, REF Quad]^;
data0 ← NARROW[par1.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
MakeHeader[dynaport: dynaport,cmd: DeMapRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data0];
SendRequest[dynaport]
};
WriteSingleRply: SimpleProc ~ {
This proc send a Write Single Reply command with the previously received parameter
address : Quad;
id: DeviceID;
data: Quad ← NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..68)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: WSRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};
WriteSingleRply1: SimpleProc ~ {
This proc send a Write Single Reply command with the given parameters
address,data : Quad;
address ← NARROW[params.first, REF Quad]^;
data ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
MakeHeader[dynaport: dynaport,cmd: WSRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};
MapRqst: SimpleProc ~ {
This proc send a Map Request command. The first parameter is the page address (Quad),
the second the aid (Quad)
address: Quad ← NARROW[params.first, REF Quad]^;
aid: Quad ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport, cmd: MapRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: aid];
SendRequest[dynaport];
};
MapReply: SimpleProc ~ {
This proc send a MapReply command with the previous received parameter.
The parameter are the flags, which are put on the 4 low order bits of the address
address: Quad;
flags: CARD;
id: DeviceID;
flags ← NARROW[params.first, REF CARD]^;
SetRQL[dynaport, Lowp, Short];
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..64)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[64..68)
DO
address[3] ← address[3]*2 + (IF (cvcardbits[flags][bit-64+28]) THEN 1 ELSE 0); --Flags
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: MapRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0]];
SendRequest[dynaport]
};
IOWriteRqst: SimpleProc ~ {
This proc send a IOWrite Request command. The first parameter is the address,
the second the Data
address: Quad ← NARROW[params.first, REF Quad]^;
data: Quad ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};
IOWriteRply: SimpleProc ~ {
This proc send a IOWrite Reply command. The first parameter is the address,
the second the Data
address: Quad ← NARROW[params.first, REF Quad]^;
data: Quad ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
MakeHeader[dynaport: dynaport,cmd: IOWRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: data];
SendRequest[dynaport]
};
IOWriteRply0: SimpleProc ~ {
This proc send a IOWrite Reply command with the previously received parameter
address: Quad;
id: DeviceID;
SetRQL[dynaport, Lowp, Short]; -- has to be low priority in order to be short.
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..68)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: IOWRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: [0,0,0,0]];
SendRequest[dynaport]
};
IOReadRqst: SimpleProc ~ {
This proc send a IORead Request command at the address "address"
address: Quad ← NARROW[params.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: IORRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,0,0] ];
SendRequest[dynaport]
};
IOReadRply: SimpleProc ~ {
This proc send a IOReadRply command at the address "address"
address: Quad ← NARROW[params.first, REF Quad]^;
data: Quad ← NARROW[params.rest.first, REF Quad]^;
SetRQL[dynaport, Lowp, Short];
MakeHeader[dynaport: dynaport,cmd: IORRply, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: data ];
SendRequest[dynaport]
};
IOReadRply0: SimpleProc ~ {
This proc send a IOReadRply with the previously received parameter (for the DevId & the address) and need on parameter more for the returned data
data: Quad ← NARROW[params.first, REF Quad]^;
address: Quad;
id: DeviceID;
SetRQL[dynaport, Lowp, Short];
address[0] ← 0;
address[1] ← 0;
address[2] ← 0;
address[3] ← 0;
id ← 0;
FOR bit:
NAT
IN[11..21)
DO
id ← id*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[36..52)
DO
address[2] ← address[2]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
FOR bit:
NAT
IN[52..68)
DO
address[3] ← address[3]*2 + (IF dynaport.ialpha[bit]=L THEN 0 ELSE 1);
ENDLOOP;
MakeHeader[dynaport: dynaport,cmd: IORRply, id: id, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: data ];
SendRequest[dynaport]
};
WaitReply: SimpleProc ~ {
This proc tests the bit "MsgHere" of status, if it is H we clear this bit in setting
and resetting the bit "ClrMsgHere". After we test if the msg was a reply :
if yes goto Nextline, if not wait an another message
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1
THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF dynaport.ialpha[8]=H
THEN NextLine[dynaport]
ELSE dynaport.countcycle ← 0;
}
}
};
WaitMapRqst: SimpleProc ~ {
This proc tests the bit "MsgHere" of status, if it is H we clear this bit in setting
and resetting the bit "ClrMsgHere". After we test if the msg was a MapRqst :
if yes goto Nextline, if not wait an another message
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, MapRqst]
THEN NextLine[dynaport]
ELSE dynaport.countcycle ← 0; --wait a new message
}
}
};
WaitReadBlockRplyandCheck: SimpleProc ~ {
This proc tests wait a ReadBlockReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, RBRply]
THEN {
IF ~CheckRcvData4[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data4"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
}
}
};
WaitIOReadRplyandCheck: SimpleProc ~ {
This proc tests wait a IOReadReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, IORRply]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitIOWRplyandCheck: SimpleProc ~ {
This proc tests wait a IOWriteReply (like WaitReply). First we test if the msg was this reply If not we wait an another message. If the msg is the good reply we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, IOWRply]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitIOWRqstandCheck: SimpleProc ~ {
This proc tests wait a IOWRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, IOWRqst]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitIOReadRqstandCheck: SimpleProc ~ {
This proc tests wait a IOReadRqst. First we test if the msg was the good command If not we wait an another message.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, IORRqst]
THEN {
IF ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitReadBlockRqstandCheck: SimpleProc ~ {
This proc tests wait a RBRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, RBRqst]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitReadBlockRqstandCheck1: SimpleProc ~ {
Same that WaitReadBlockRqstandCheck but without the testing of the second word.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, RBRqst]
THEN {
IF ~CheckRcvData0[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitWriteSingleRqstAndCheck: SimpleProc ~ {
This proc tests wait a WSRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, WSRqst]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitCondWriteSingleRqstAndCheck: SimpleProc ~ {
This proc tests wait a CondWSRqst. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, CWSRqst]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
WaitCondWriteSingleRplyAndCheck: SimpleProc ~ {
This proc tests wait a CondWSRply. First we test if the msg was the good command If not we wait an another message. If the msg is the good command we test the data. If the data is OK then we goto Nextline, if not we send a signal.
IF dynaport.status[MsgHere] = H
AND dynaport.countcycle =0
THEN {
dynaport.countcycle ← 1;
dynaport.rqlar[ClrMsgHere] ← H;
dynaport.load ← H }
ELSE
IF dynaport.countcycle=1 THEN dynaport.countcycle 𡤂
ELSE {
IF (1 < dynaport.countcycle) AND (dynaport.countcycle < 6)
--for wait all the message
THEN{
dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[ClrMsgHere] ← L
}
ELSE
IF dynaport.countcycle=6
THEN{
dynaport.load ← L;
IF CheckRcvCom[dynaport, CWSRply]
THEN {
IF ~CheckRcvData1[dynaport, params] THEN SIGNAL DynaBusEvent["Error DynaBus compare data1"];
NextLine[dynaport]}
ELSE dynaport.countcycle ← 0; --wait a new message
};
}
};
Special Memory Controller Commands
IOWrite0 : SimpleProc~ {
This proc send a IOWrite Request command in the register of address "00300400H", with value a
data computed by MCUtils.ComposeIOWrite0
data, data0, data3, data4, data5, data6, data7, data8: CARD;
data1, data2: BOOL;
address: Quad ← [0,0,30H,0400H];
par1: LIST OF REF ANY ← params;
data0 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF BOOL]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF BOOL]^; par1 ← par1.rest;
data3 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data4 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data5 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data6 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data7 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data8 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
SetRQL[dynaport, Lowp, Short];
data← MCUtils.ComposeIOWrite0[ownerFifoDelay: data0, enbCorr: data1, enbOpReflect: data2, selRefCk: data3, gntDelay: data4, pchgDelay: data5, refDelay: data6, wrDelay: data7, rdDelay: data8];
MakeHeader[dynaport: dynaport, cmd: IOWRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data],Basics.LowHalf[data]] ];
SendRequest[dynaport]
};
IOWrite1 : SimpleProc~ {
This proc send a IOWrite Request command in the register of address "00300401H", with
a data value computed by MCUtils.ComposeIOWrite1
data, data0, data1, data2, data3 : CARD;
address: Quad ← [0,0,30H,0401H];
par1: LIST OF REF ANY ← params;
data0 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data3 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
SetRQL[dynaport, Lowp, Short];
data ← MCUtils.ComposeIOWrite1[banks: data0, ramAddWires: data1, bankAdd: data2, pageAdd: data3];
MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport,d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]];
SendRequest[dynaport]
};
IOWrite2 : SimpleProc~ {
This proc send a IOWrite Request command in the register of address "00300402H", with
a data value computed by MCUtils.ComposeIOWrite2
data, data0, data1, data2 : CARD;
address: Quad ← [0,0,30H,0402H];
par1: LIST OF REF ANY ← params;
data0 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data1 ← NARROW[par1.first, REF CARD]^; par1 ← par1.rest;
data2 ← NARROW[par1.first, REF CARD]^;
SetRQL[dynaport, Lowp, Short];
data← MCUtils.ComposeIOWrite2[banks: data0, ramAddWires: data1, bankAdd: data2];
MakeHeader[dynaport: dynaport,cmd: IOWRqst, add: address, mode: FALSE];
MakeData1[dynaport: dynaport, d0: [0,0,Basics.HighHalf[data], Basics.LowHalf[data]]];
SendRequest[dynaport]
};
SendShOw : SimpleProc~ {
This proc activates the Shared line, Owner line or both, depending of the
parameter which is a Rope which value is "S", "O" or "SO"
SO: Rope.ROPE ← NARROW[params.first, REF Rope.ROPE]^;
SELECT dynaport.countcycle
FROM
0 => { dynaport.countcycle ← dynaport.countcycle+1;
SELECT
TRUE
FROM
Rope.Equal[SO, "S"] => dynaport.rqlar[bitShared] ← H; --bit Shared
Rope.Equal[SO, "O"] => dynaport.rqlar[bitOwner] ← H; --bit bitOwner
Rope.Equal[SO, "SO"] => {dynaport.rqlar[bitOwner] ← H; dynaport.rqlar[bitShared]← H};
ENDCASE => ERROR;
dynaport.load ← H; };
1 => { dynaport.countcycle ← dynaport.countcycle+1;
dynaport.rqlar[bitShared] ← L;
dynaport.rqlar[bitOwner] ← L};
ENDCASE => {dynaport.countcycle ← dynaport.countcycle+1;
dynaport.load ← L;
NextLine[dynaport] };
};
C: PROC [c: CARD] RETURNS [rc: REF ANY] = {rc ← NEW[CARD ← c]};
Q: PROC [c: Quad] RETURNS [rc: REF ANY] = {rc ← NEW[Quad ← c]};
Simulation Procs
SendBus:
PUBLIC
PROC [dynaport: Dyn.DynaPortState]
RETURNS [] ~ {
IF dynaport.testProcList =
NIL
THEN {
dynaport.testProcList ← NARROW[Atom.GetProp[$Simul2Sender, $PKList]];
};
DO
AtomDidSomething:
PROC [atom:
ATOM, params:
LIST
OF
REF
ANY]
RETURNS [
BOOL] =
{
v: REF ANY = Atom.GetProp[$Simul2Sender, atom];
IF v #
NIL
THEN {
spr: REF SimpleProc = NARROW[v];
spr^[dynaport, params];
RETURN[TRUE];
}
ELSE {
NextLine[dynaport];
RETURN[FALSE];
};
};
WITH dynaport.testProcList.first
SELECT
FROM
atom: ATOM => IF AtomDidSomething[atom, NIL] THEN EXIT;
list:
LIST
OF
REF
ANY => {
WITH list.first
SELECT
FROM
atom: ATOM => IF AtomDidSomething[atom, list.rest] THEN EXIT;
ENDCASE => ERROR;
};
ENDCASE => ERROR;
ENDLOOP;
};
Atom.PutProp[$Simul2Sender, $Init, NEW[SimpleProc ← Init]];
Atom.PutProp[$Simul2Sender, $ReceiveAll, NEW[SimpleProc ← ReceiveAll]];
Atom.PutProp[$Simul2Sender, $StartStop, NEW[SimpleProc ← StartStop]];
Atom.PutProp[$Simul2Sender, $Wait, NEW[SimpleProc ← Wait]];
Atom.PutProp[$Simul2Sender, $WaitMsgSent, NEW[SimpleProc ← WaitMsgSent]];
Atom.PutProp[$Simul2Sender, $WaitMsgReceived, NEW[SimpleProc ← WaitMsgReceived]];
Atom.PutProp[$Simul2Sender, $Jump, NEW[SimpleProc ← Jump]];
Atom.PutProp[$Simul2Sender, $WaitSync, NEW[SimpleProc ← WaitSync]];
Atom.PutProp[$Simul2Sender, $SetFlag, NEW[SimpleProc ← SetFlag]];
Atom.PutProp[$Simul2Sender, $ClearFlag, NEW[SimpleProc ← ClearFlag]];
Atom.PutProp[$Simul2Sender, $SkipIfTrue, NEW[SimpleProc ← SkipIfTrue]];
Atom.PutProp[$Simul2Sender, $StopSimul, NEW[SimpleProc ← StopSimul]];
DynaBus Commands
Atom.PutProp[$Simul2Sender, $WriteBlockRqst, NEW[SimpleProc ← WriteBlockRqst]];
Atom.PutProp[$Simul2Sender, $ReadBlockRqst, NEW[SimpleProc ← ReadBlockRqst]];
Atom.PutProp[$Simul2Sender, $ReadBlockRply, NEW[SimpleProc ← ReadBlockRply]];
Atom.PutProp[$Simul2Sender, $WriteSingleRqst, NEW[SimpleProc ← WriteSingleRqst]];
Atom.PutProp[$Simul2Sender, $WriteSingleRply, NEW[SimpleProc ← WriteSingleRply]];
Atom.PutProp[$Simul2Sender, $WriteSingleRply1, NEW[SimpleProc ← WriteSingleRply1]];
Atom.PutProp[$Simul2Sender, $FlushBlockRqst, NEW[SimpleProc ← FlushBlockRqst]];
Atom.PutProp[$Simul2Sender, $CondWSRqst, NEW[SimpleProc ← CondWSRqst]];
Atom.PutProp[$Simul2Sender, $CondWSRply, NEW[SimpleProc ← CondWSRply]];
Atom.PutProp[$Simul2Sender, $CondWSRply1, NEW[SimpleProc ← CondWSRply1]];
Atom.PutProp[$Simul2Sender, $DeMapRqst, NEW[SimpleProc ← DeMapRqst]];
Atom.PutProp[$Simul2Sender, $DeMapRply, NEW[SimpleProc ← DeMapRply]];
Atom.PutProp[$Simul2Sender, $DeMapRply1, NEW[SimpleProc ← DeMapRply1]];
Atom.PutProp[$Simul2Sender, $WaitMapRqst, NEW[SimpleProc ← WaitMapRqst]];
Atom.PutProp[$Simul2Sender, $MapReply, NEW[SimpleProc ← MapReply]];
Atom.PutProp[$Simul2Sender, $IOReadRqst, NEW[SimpleProc ← IOReadRqst]];
Atom.PutProp[$Simul2Sender, $IOReadRply, NEW[SimpleProc ← IOReadRply]];
Atom.PutProp[$Simul2Sender, $IOReadRply0, NEW[SimpleProc ← IOReadRply0]];
Atom.PutProp[$Simul2Sender, $MapRqst, NEW[SimpleProc ← MapRqst]];
Atom.PutProp[$Simul2Sender, $IOWriteRqst, NEW[SimpleProc ← IOWriteRqst]];
Atom.PutProp[$Simul2Sender, $IOWriteRply, NEW[SimpleProc ← IOWriteRply]];
Atom.PutProp[$Simul2Sender, $IOWriteRply0, NEW[SimpleProc ← IOWriteRply0]];
Atom.PutProp[$Simul2Sender, $WaitReply, NEW[SimpleProc ← WaitReply]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRplyandCheck, NEW[SimpleProc ← WaitReadBlockRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOReadRplyandCheck, NEW[SimpleProc ← WaitIOReadRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOWRplyandCheck, NEW[SimpleProc ← WaitIOWRplyandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOWRqstandCheck, NEW[SimpleProc ← WaitIOWRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitIOReadRqstandCheck, NEW[SimpleProc ← WaitIOReadRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck, NEW[SimpleProc ← WaitReadBlockRqstandCheck]];
Atom.PutProp[$Simul2Sender, $WaitReadBlockRqstandCheck1, NEW[SimpleProc ← WaitReadBlockRqstandCheck1]];
Atom.PutProp[$Simul2Sender, $WaitWriteSingleRqstAndCheck, NEW[SimpleProc ← WaitWriteSingleRqstAndCheck]];
Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRqstAndCheck, NEW[SimpleProc ← WaitCondWriteSingleRqstAndCheck]];
Atom.PutProp[$Simul2Sender, $WaitCondWriteSingleRplyAndCheck, NEW[SimpleProc ← WaitCondWriteSingleRplyAndCheck]];
Special Memory Controller Commands
Atom.PutProp[$Simul2Sender, $IOWrite0, NEW[SimpleProc ← IOWrite0]];
Atom.PutProp[$Simul2Sender, $IOWrite1, NEW[SimpleProc ← IOWrite1]];
Atom.PutProp[$Simul2Sender, $IOWrite2, NEW[SimpleProc ← IOWrite2]];
Atom.PutProp[$Simul2Sender, $SendShOw, NEW[SimpleProc ← SendShOw]];
Atom.PutProp[$Simul2Sender, $PKList,
LIST[
$Init,
$Nop,
LIST[$Jump, $Nop]
]];
END.
Change Log
4-28-88: Change IOAddress of IOWrite0, IOWrite1, and IOWrite2 to be consistent with having the Memory Controller have DynaBusId=1 (not 0).
4-29-88: Added $IOWriteRply command. JHH.